• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.879-882
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• 2003

Differential Power Analysis(DPA) is powerful attack method for smart card. Self-timed circuit has several advantages resisting to DPA. In that reason, DPA countermeasure using self-timed circuit is thought as one of good solution for DPA prevention. In this paper, we examine what self-timed features are good against DPA, and how much we can get benefit from it. Also we test several self-timed circuit implementation style in order to compare DPA resistance factor. Simulation results show that self-timed circuit is more resistant to DPA than conventional synchronous circuit, and can be used for designing cryptographic hardware for smart-card.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.379-382
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• 2000

We designed a self-timed interface circuit for efficient communication in IP (Intellectual Property)-based system with high-speed self-timed FIFO and a set of self-timed event logic library with 0.25um CMOS technology. Optimized self-timed standard cell layouts and Verilog models are generated for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. With clock control method and FIFO, we implemented high-speed 32bit-interface chip for self-timed system, which generated maximum system clock is 2.2GHz. The size of the core is about 1.1mm x 1.1mm.

• Physical Therapy Rehabilitation Science
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• 제10권3호
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• pp.257-262
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• 2021

Objective: Patients with stroke generally diminished ankle range of motion, which decreases balance and walking ability. This study aimed to determine the effect of ankle self-mobilization with movement (s-MWM) on ankle dorsiflexion passive range of motion, timed up and go test, and dynamic gait index in patients with chronic stroke. Design: Randomized controlled trial design Methods: Twenty-four post-stroke patients participated in this study. The participants were randomized into the control (n = 12) and self-MWM groups (n = 12). Both groups attended standard rehabilitation therapy for 30 minutes per session. In addition, self-MWM group was performed 3 times per week for 8 weeks. All participants have measured ankle dorsiflexion passive range of motion, timed up and go test, and dynamic gait index in before and after the intervention. Results: After 8 weeks of training, self-MWM group showed greater improvement in ankle dorsiflexion passive range of motion, timed up and go test, and dynamic gait index than in the control group (p<0.05). Further, self-MWM group had significantly improvement in all dependent variables compared to the pre-test (p<0.05). Conclusions: Our investigation demonstrates that self-MWM is beneficial for improving functional ability. Also, self-MWM was superior to control with respect to improving ankle dorsiflexion passive range of motion, timed up and go test, and dynamic gait index.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.534-537
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• 1998

In this paper, a set of novel self-timed latches are introduced and analyzed. These latches have no back-to-back connection as in conventional self-timed latch, and both inverting and noninerting outputs are evaluated simultaneously leading to thigher oepating frequencies. Power consumption of these latches ar ealso comparable to or less than that of conventional circuits. Novel type of cross-coupled inverter used in the proosed circuits implements static operatin without signal fighting with the main driver during signal transition. Proposed latches ar tested using a 0.6.mu.m triple-poly triple-metal n-well CMOS technology. The resutls indicates that proposed active-low sefl-timed latch (ALSTL) improves speed by 14-34% over conventional NAND SR latch, while in active-high self-timed latch (AHSTL) the improvements are 15-35% with less power as compared with corresponding NORA SR latch. These novel latches have been successfully implemented in a high-speed synchronous DRAM (SDRAM).

• 전자공학회논문지B
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• 제31B권5호
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• pp.81-87
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• 1994

This paper proposes a divider structure that combines a carry-propagation-free division algorithm using RSD number system and a self-timed ring structure. The self-timed ring structure enables the divider to compute at a speed comparable to that of combinational array dividers with less silicon area. By exploiting the carry-propagation-free division algorithm, we can achieve further reduction of silicon area and computation time. The algorithm and structure of the proposed divider have been successfully verified through VHDL modeling and simulation. Preliminary experimental results show the effectiveness of the algorithm and structure.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 B
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• pp.666-668
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• 1998

In this paper we illustrate the design of a node label data flow machine based on self-timed paradigm. Data flow machines differ from most other parallel architectures, they are based on the concept of the data-driven computation model instead of the program store computation model. Since the data-driven computation model provides the excution of instructions asynchronously, it is natural to implement a data flow machine using self timed circuits.

• 한국정보통신학회논문지
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• 제24권2호
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• pp.268-275
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• 2020

정보보안 응용에 적합한 self-timed 링 (ring) 기반 TRNG (true random number generator)의 경량 하드웨어 설계에 관해 기술한다. TRNG의 하드웨어 복잡도를 줄이기 위해 피드백 구조의 엔트로피 추출기를 제안하였으며, 이를 통해 링 스테이지 수를 최소화 하였다. 본 논문의 FSTR-TRNG는 동작 주파수와 엔트로피 추출 회로를 고려하여 링 스테이지 수가 11의 배수가 되도록 결정되었으며, 링 발진기가 등간격 모드로 진동할 수 있도록 토큰 (token)과 버블(bubble) 개수의 비를 결정하였다. FSTR-TRNG는 FPGA 디바이스에 구현하여 난수 생성 동작을 검증하였다. Spartan-6 FPGA 디바이스에 구현된 FSTR-TRNG로부터 2,000만 비트의 데이터를 추출하여 NIST SP 800-22에 규정된 통계학적 무작위성 테스트를 수행한 결과, 15개의 테스트가 모두 기준을 만족하는 것으로 확인되었다. Spartan-6 FPGA 디바이스로 합성한 FSTR-TRNG는 46 슬라이스로 구현이 되었으며, 180 nm CMOS 표준셀로 합성하는 경우에는 약 2,500 등가 게이트로 구현되었다.

• 전자공학회논문지C
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• 제35C권7호
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• pp.37-45
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• 1998

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

• 대한전자공학회논문지SD
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• 제45권8호
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• pp.37-43
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• 2008

본 논문에서는 고속 동작에서 동적 전력 소비와 정적 전력 소비를 동시에 줄일 수 있는 self-timed current-mode Logic(STCML)을 제안한다. 제안된 로직 스타일은 펄스 신호로 가상 접지를 방전하여 로직 게이트의 누설 전류(subthreshold leakage current)를 획기적으로 감소시켰다. 또한, 본 로직은 개선된 self-timing buffer를 사용하여 동적모드 동작 시 발생되는 단락 회로 전류(short-circuit current)를 최소화하였다. 80-nm CMOS 공정을 이용하여 실시한 비교 실험 결과, 제안된 로직 스타일은 기존의 대표적인 current-mode logic인 DyCML에 비하여 동일한 시간 지연에서 26 배의 누설 전력 소비를 줄이고 27%의 동적 전력 소비를 줄일 수 있었다. 또한, 대표적인 디지털 로직 스타일인 DCVS와의 비교 결과, 59%의 누설 전력 소비감소 효과가 있었다.

• 대한지역사회작업치료학회지
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• 제3권2호
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• pp.25-32
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• 2013

목적 : 본 연구는 일반노인에게 시각적 피드백에 따른 발목 움직임 조절 도구를 사용하여 자가 운동을 시행하였을 때 노인의 발목 움직임 조절과 균형능력에 미치는 영향을 알아보고자 하였다. 연구방법 : 이 연구는 사례 연구(case-study)로써, 사전-사후 검사를 실시하였다. 80세인 일반 여성 노인에게 2주 동안 매일 오전, 오후 20분 동안 자가 운동을 실시하였다. 사전, 사후 검사로는 발목 조절 움직임 평가를 위한 Tracking 검사, 균형 능력 측정을 위한 한발로 서기 시간 측정과 Timed up-And-Go검사를 시행하였다. 결과 : 대상자는 Tracking 검사에서 발목 조절 움직임의 향상을 보였다. 균형 능력 평가에서는 한발로 서기유지 시간은 증가하였으나, Timed up-And-Go검사는 변화가 없었다. 결론 : 시각적 피드백에 따른 발목 조절 움직임 도구를 이용한 자가 운동은 노인의 발목 움직임 조절과 균형을 향상 시켰다.