• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.879-882
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• 2003

Differential Power Analysis(DPA) is powerful attack method for smart card. Self-timed circuit has several advantages resisting to DPA. In that reason, DPA countermeasure using self-timed circuit is thought as one of good solution for DPA prevention. In this paper, we examine what self-timed features are good against DPA, and how much we can get benefit from it. Also we test several self-timed circuit implementation style in order to compare DPA resistance factor. Simulation results show that self-timed circuit is more resistant to DPA than conventional synchronous circuit, and can be used for designing cryptographic hardware for smart-card.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.379-382
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• 2000

We designed a self-timed interface circuit for efficient communication in IP (Intellectual Property)-based system with high-speed self-timed FIFO and a set of self-timed event logic library with 0.25um CMOS technology. Optimized self-timed standard cell layouts and Verilog models are generated for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. With clock control method and FIFO, we implemented high-speed 32bit-interface chip for self-timed system, which generated maximum system clock is 2.2GHz. The size of the core is about 1.1mm x 1.1mm.

• Physical Therapy Rehabilitation Science
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• v.10 no.3
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• pp.257-262
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• 2021

Objective: Patients with stroke generally diminished ankle range of motion, which decreases balance and walking ability. This study aimed to determine the effect of ankle self-mobilization with movement (s-MWM) on ankle dorsiflexion passive range of motion, timed up and go test, and dynamic gait index in patients with chronic stroke. Design: Randomized controlled trial design Methods: Twenty-four post-stroke patients participated in this study. The participants were randomized into the control (n = 12) and self-MWM groups (n = 12). Both groups attended standard rehabilitation therapy for 30 minutes per session. In addition, self-MWM group was performed 3 times per week for 8 weeks. All participants have measured ankle dorsiflexion passive range of motion, timed up and go test, and dynamic gait index in before and after the intervention. Results: After 8 weeks of training, self-MWM group showed greater improvement in ankle dorsiflexion passive range of motion, timed up and go test, and dynamic gait index than in the control group (p<0.05). Further, self-MWM group had significantly improvement in all dependent variables compared to the pre-test (p<0.05). Conclusions: Our investigation demonstrates that self-MWM is beneficial for improving functional ability. Also, self-MWM was superior to control with respect to improving ankle dorsiflexion passive range of motion, timed up and go test, and dynamic gait index.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.534-537
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• 1998

In this paper, a set of novel self-timed latches are introduced and analyzed. These latches have no back-to-back connection as in conventional self-timed latch, and both inverting and noninerting outputs are evaluated simultaneously leading to thigher oepating frequencies. Power consumption of these latches ar ealso comparable to or less than that of conventional circuits. Novel type of cross-coupled inverter used in the proosed circuits implements static operatin without signal fighting with the main driver during signal transition. Proposed latches ar tested using a 0.6.mu.m triple-poly triple-metal n-well CMOS technology. The resutls indicates that proposed active-low sefl-timed latch (ALSTL) improves speed by 14-34% over conventional NAND SR latch, while in active-high self-timed latch (AHSTL) the improvements are 15-35% with less power as compared with corresponding NORA SR latch. These novel latches have been successfully implemented in a high-speed synchronous DRAM (SDRAM).

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.81-87
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• 1994

This paper proposes a divider structure that combines a carry-propagation-free division algorithm using RSD number system and a self-timed ring structure. The self-timed ring structure enables the divider to compute at a speed comparable to that of combinational array dividers with less silicon area. By exploiting the carry-propagation-free division algorithm, we can achieve further reduction of silicon area and computation time. The algorithm and structure of the proposed divider have been successfully verified through VHDL modeling and simulation. Preliminary experimental results show the effectiveness of the algorithm and structure.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.666-668
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• 1998

In this paper we illustrate the design of a node label data flow machine based on self-timed paradigm. Data flow machines differ from most other parallel architectures, they are based on the concept of the data-driven computation model instead of the program store computation model. Since the data-driven computation model provides the excution of instructions asynchronously, it is natural to implement a data flow machine using self timed circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.268-275
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• 2020

A lightweight hardware design of self-timed ring based true random number generator (TRNG) suitable for information security applications is described. To reduce hardware complexity of TRNG, an entropy extractor with feedback structure was proposed, which minimizes the number of ring stages. The number of ring stages of the FSTR-TRNG was determined to be a multiple of eleven, taking into account operating clock frequency and entropy extraction circuit, and the ratio of tokens to bubbles was determined to operate in evenly-spaced mode. The hardware operation of FSTR-TRNG was verified by FPGA implementation. A set of statistical randomness tests defined by NIST 800-22 were performed by extracting 20 million bits of binary sequences generated by FSTR-TRNG, and all of the fifteen test items were found to meet the criteria. The FSTR-TRNG occupied 46 slices of Spartan-6 FPGA device, and it was implemented with about 2,500 gate equivalents (GEs) when synthesized in 180 nm CMOS standard cell library.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.37-45
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• 1998

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.37-43
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• 2008

This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).

• The Journal of Korean society of community based occupational therapy
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• v.3 no.2
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• pp.25-32
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• 2013

Objective : The purpose of this study was to investigate the effect of the ankle movement and the balance when the elderly conducted self-exercise with ankle movement control device through visual feedback. Method : This case-study included pre-test and post-test. The elderly women aged 80 did self-exercise for 20 minutes both morning and afternoon every day. The pre-test and post-test was conducted tracking test for evaluating ankle control movement and running time measurement of standing on one foot and Timed up-And-Go test for balance. Result : The subject improved the ankle control movement on tracking test and improved the balance in running time measurement of standing on one foot. But, Timed up-And-Go test was no change. Conclusion : The self-exercise with device of ankle movement control through visual feedback improved the ankle control movement and the balance for elderly.