• 대한기계학회논문집A
• /
• 제34권10호
• /
• pp.1529-1535
• /
• 2010

생산 장비로서 잉크젯 기술의 신뢰성을 증대 시키기 위하여 잉크젯 헤드의 작동 상태를 모니터링하고 이상 유무를 즉시 발견 할 수 있는 소프트웨어 및 하드웨어를 개발 하였다. 잉크젯 헤드의 작동 상태의 측정을 위하여 잉크젯 헤드의 피에조 전기 신호를 사용하였다. 이를 위하여 피에조의 변형량을 간접적으로 측정 할 수 있는 회로를 개발 하였고, 측정된 전기 신호를 사용하여 작동의 불량 여부를 판단 할 수 있도록 소프트웨어 알고리즘을 개발하였다. 또한 다중 노즐 헤드에 적용이 가능하도록 소프트웨어 개발 및 시스템 통합을 수행하였다.

• 대한의용생체공학회:의공학회지
• /
• 제31권2호
• /
• pp.87-93
• /
• 2010

Researches for stem cells have been focused on scientists in biomedical sciences as well as clinical application for its great therapeutic potentials. Stem cells have two distinct characteristics: self-renewal and differentiation. In this short review, the links between stem cell research and biomedical engineering is discussed based on the basic characteristics of stem cells. This concept can be extended to the fundamental questions of biological sciences for cells such as proliferation, apoptosis, differentiation, and migration. For understanding proliferation and apoptosis of stem cells, techniques from biomedical engineering such as surface patterning, MEMS, nanotechnologies have been used. The advanced technologies such as microfluidic technologies, three dimensional scaffold fabrication, and mechanical/electrical stimulation have also been used in cell differentiation and migration. Basic and unsolved questions in the stem cell research field have limitations by studying conventional technologies. Therefore, the strategic fusion between stem cell biology and novel biomedical engineering field will break the barriers for understanding fundamental questions of stem cells, which can open the window for the clinical applications of stem cell based therapeutics as well as regeneration of damaged tissues.

• 한국기계가공학회지
• /
• 제2권4호
• /
• pp.17-24
• /
• 2003

Chemical mechanical polishing(CMP) has been applied for planarization of topography after patterning process in semiconductor fabrication process. Tungsten CMP is necessary to build up interconnects of semiconductor device. But the tungsten dishing and the oxide erosion defects appear at end-point during tungsten CMP. It has been known that the generation of dishing and erosion is based on the over-polishing time, which is determined by pattern selectivity. Fixed abrasive pad takes advantage of decreasing the defects resulting flam reducing pattern selectivity because of the lower abrasive concentration. The manufacturing technique of fixed abrasive pad using hydrophilic polymers is introduced in this paper. For application to tungsten CMP, chemicals composed of oxidizer, catalyst, and acid were developed. In comparison of the general pad and slurry for tungsten CMP, the fixed abrasive pad and the chemicals resulted in appropriate performance in point of removal rate, uniformity, material selectivity and roughness.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
• /
• pp.211.1-211.1
• /
• 2014

Recently, the scaling of conventional planar NAND flash devices is facing its limits by decreasing numbers of electron stored in the floating gate and increasing difficulties in patterning. Three-dimensional vertical NAND devices have been proposed to overcome these issues. Atomic layer deposition (ALD) is the most promising method to deposit charge trap layer of vertical NAND devices, SiN, with excellent quality due to not only its self-limiting growth characteristics but also low process temperature. ALD of silicon nitride were studied using NH3 and silicon chloride precursors, such as SiCl4[1], SiH2Cl2[2], Si2Cl6[3], and Si3Cl8. However, the reaction mechanism of ALD silicon nitride process was rarely reported. In the present study, we used density functional theory (DFT) method to calculate the reaction of silicon chloride precursors with a silicon nitride surface. DFT is a quantum mechanical modeling method to investigate the electronic structure of many-body systems, in particular atoms, molecules, and the condensed phases. The bond dissociation energy of each precursor was calculated and compared with each other. The different reactivities of silicon chlorides precursors were discussed using the calculated results.

• 한국재료학회지
• /
• 제17권5호
• /
• pp.273-277
• /
• 2007

Vertically aligned Zinc Oxide rod arrays were grown by the self-assembly hydrothermal process on the GaN epitaxial layer which has a same lattice structure with ZnO. Zinc nitrate and DETA solutions are used in the hydrothermal process. The $(HfO_2)$ thin film was deposited on GaN and the patterning was made by the photolithography technique. The selective growth of ZnO rod was achieved with the patterned GaN substrate. The fabricated ZnO rods are single crystal, and have grown along hexagonal c-axis direction of (002) which is the same growth orientation of GaN epitaxial layer. The density and the size of ZnO rod can be controlled by the pattern. The optical property of ordered array of vertical ZnO rods will be discussed in the present work.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 추계학술대회 논문집
• /
• pp.514-514
• /
• 2007

1차원 구조를 갖는 나노 와이어들은 나노 소자를 구현하기 위한 building-block으로 많은 과학자들의 주목을 받고 있고 또한 연구되고 있다. 하지만 그것을 정확하게 위치시키고 일정한 간격으로 정렬시키기 위한 기술 개발은 아직도 해결해야 할 큰 과제로 남아 있다. 이 논문에서, 우리는 ahsing 기술과 표면 패터닝 기술을 이용하여 대면적의 실리콘웨이퍼 위에 DNA(deoxyribonucleic acid)를 기반으로 한 금 나노 와이어를 정확하게 위치시키고 일정한 간격으로 정렬시킬 수 있는 새로운 제어 기술을 제안한다. 먼저 우리는 포토 리소그래피 공정과 $O_2$ 플라즈마 ashing 기술을 이용하여 선폭을 100 nm로 감소 시켰다. 그리고 자기조립단분자막 (self-assembled monolayers; SAMs) 방법과 lift-off 공정을 반복함으로서 1-octadecyltrichlorosilane(OTS) 층과 aminopropylethoxysilane(APS) 층을 형성하였다. 마지막으로 DNA 용액을 샘플 표면 위에 도포하고 분자 빗질 방법으로 DNA를 한 방향으로 정렬 시켰고 금 나노입자 용액을 처리하였다. 그 결과 금 나노 와이어는 $10{\mu}m$ 간격으로 일정하게 정열 되었고, APS 층에만 정확하게 정렬되었다. 우리는 금 나노 와이어를 관찰하기 위하여 원자간력 현미경 (Atomic Force Microscope AFM)을 사용하였다.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2009년도 제38회 동계학술대회 초록집
• /
• pp.248-248
• /
• 2010

CMOS 축소화가 32nm node를 넘어서 지속적으로 진행되기 위하여 FinFET, Surround Gate and Tri-Gate와 같은 Fully Depleted 3-Dimensional 소자들이 SCE를 다루기 위해서 많이 제안되어 왔다. 하지만 소자의 축소화를 진행함에 있어서 좁고 균일한 patterning을 형성하는 것과 동시에 낮은 Extension Region과 Contact Region에서의 Series Resistance을 제공하여야 하고 Source/Drain Contact Formation을 확보하여야 한다. 그리고 소자의 축소화가 진행됨으로써 Silicide의 응집현상과 Source/Drain Junction의 누설전류에 대한 허용범위가 점점 엄격해지고 있다. ITRS 2005에 따르면 32nm CMOS에서는 Contact Resistivity가 대략 $2{\times}10-8{\Omega}cm2$이 요구되고 있다. 또한 Three Dimensional 소자에서는 Fin Corner Effect가 Channel Region뿐만 아니라 S/D Region에서도 중대한 영향을 미치게 된다. 따라서 본 논문에서 제시하는 Novel S/D Contact Formation 기술을 이용하여 Self-Aligned Dual/Single Metal Contact을 이루어Patterning에 대한 문제점 해결과 축소화에 따라 증가하는 Contact Resistivity 문제점을 해결책을 제시하고자 한다. 이를 검증하기3D MOSFET제작하고 본 기술을 적용하고 검증한다. 또한 Normal Doping 구조를 가진3D MOSFET뿐만 아니라 SCE를 해결하기 위해서 대안으로 제시되고 있는 SB-MOSFET을 3D 구조로 제작하고, 이 기술을 적용하여 검증한다. 그리고 Silvaco simulation tool을 이용하여 S/D에 Metal이 Contact을 이루는 구조가 Double type과 Triple type에 따라 Contact Resistivity에 미치는 영향을 미리 확인하였고 이를 실험으로 검증하여 소자의 축소화에 따라 대두되는 문제점들의 해결책을 제시하고자 한다.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2010년도 제39회 하계학술대회 초록집
• /
• pp.65-65
• /
• 2010

Extreme ultraviolet lithography (EUVL) is expected to be applied for making patterns below 32 nm in device industry. An ultrathin EUV photoresist (PR) of a few nm in thickness is required to reduce minimum feature size further. Here, we show that pentacene molecular layers can be employed as a new EUV resist for the first time. Dots and lines in nm scale are successfully realized using the new molecular resist. We clearly provide the mechanism for forming the nanopatterns with scanning photoemission microscope (SPEM), EUV interference lithography (EUV-IL), atomic force microscope (AFM), photoemission spectroscopy (PES), etc. The molecular PR has several advantages over traditional polymer EUV PRs; for example, high thermal/chemical stability, negligible outgassing, ability to control the height and width on the nanometer scale, leaving fewer residuals, no need for a chemical development process and thus reduction of chemical waste to make the nanopatterns. Besides, it could be applied to any substrate to which pentacene bonds chemically, such as $SiO_2$, SiN, and SiON, which is of importance in the device industry.

• 한국자기학회:학술대회 개요집
• /
• 한국자기학회 2010년도 임시총회 및 하계학술연구발표회
• /
• pp.79-79
• /
• 2010

Semimetallic bismuth (Bi) has been extensively investigated over the last decade since it exhibits very intriguing transport properties due to their highly anisotropic Fermi surface, low carrier concentration, long carrier mean free path l, and small effective carrier mass $m^*$. In particular, the great interest in Bi nanowires lies in the development of nanowire fabrication methods and the opportunity for exploring novel low-dimensional phenomena as well as practical application such as thermoelectricity[1]. In this work, we introduce a self-assembled interconnection of nanostructures produced by an on-film formation of nanowires (OFF-ON) method in order to form a highly ohmic Bi nanobridge. A Bi thin film was first deposited on a thermally oxidized Si (100) substrate at a rate of $40\;{\AA}/s$ by radio frequency (RF) sputtering at 300 K. The sputter system was kept in an ultra high vacuum (UHV) of $10^{-6}$ Torr before deposition, and sputtering was performed under an Ar gas pressure of 2m Torr for 180s. For the lateral growth of Bi nanowires, we sputtered a thin Cr (or $SiO_2$) layer on top of the Bi film. The Bi thin films were subsequently put into a custom-made vacuum furnace for thermal annealing to grow Bi nanowires by the OFF-ON method. After thermal annealing, the Bi nanowires cannot be pushed out from the topside of the Bi films due to the Cr (or $SiO_2$) layer. Instead, Bi nanowires grow laterally as a mean s of releasing the compressive stress. We fabricated a self-assembled Bi nanobridge (d=192 nm) device in-situ using OFF-ON through annealing at $250^{\circ}C$ for 10hours. From I-V measurements taken on the Bi nanobridge device, contacts to the nanobridge were found highly ohmic. The quality of the Bi nanobridge was also proved by the high MR of 123% obtained from transverse MR measurements. These results manifest the possibility of self-assembled nanowire interconnection between various nanostructures for a variety of applications and provide a simple device fabrication method to investigate transport properties on nanowires without complex patterning and etching processes.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
• /
• pp.237.1-237.1
• /
• 2016

Electrical properties of graphene-based field effect transistors (G-FETs) can be degraded in ambient conditions owing to physisorbed oxygen or water molecules on the graphene surface. Passivation technique is one of a fascinating strategy for fabrication of G-FETs, which allows to sustain electrical properties of graphene in the long term without disrupting its inherent properties: transparency, flexibility and thinness. Ironically, despite its importance in producing high performance graphene devices, this method has been much less studied compared to patterning or device fabrication processes. Here we report a novel surface passivation method by using atomically thin self-assembled alkane layers such as C18- NH2, C18-Br and C36 to prevent unintentional doping effects that can suppress the degradation of electrical properties. In each passivated device, we observe a shift in charge neutral point to near zero gate voltage and it maintains the device performance for 1 year. In addition, the fabricated PG-FETs on a plastic substrate with ion-gel gate dielectrics exhibit not only mechanical flexibility but also long-term stability in ambient conditions. Therefore, we believe that these highly transparent and ultra-thin passivation layers can become a promising candidate in a wide range of graphene based electronic applications.