• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.293-303
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• 2008

As the computing environment moves to the wireless and handheld system, the power efficiency is getting more important. That is the case especially in the embedded hand-held system and the power consumed by the memory system takes the second largest portion in overall. To save energy consumed in the memory system we can utilize low power mode of SDRAM. In the case of RDRAM, nap mode consumes less than 5% of the power consumed in active or standby mode. However hardware controller itself can't use this facility efficiently unless the operating system cooperates. In this paper we focus on how to minimize the number of active units of SDRAM. The operating system allocates its physical pages so that only a few units of SDRAM need to be activated and the unnecessary SDRAM can be put into nap mode. This work can be considered as a generalized and system-wide version of PAVM(Power-Aware Virtual Memory) research. We take all the physical memory into account, especially buffer cache, which takes an half of total memory usage on average. Because of the portion of buffer cache and its importance, PAVM approach cannot be robust without taking the buffer cache into account. In this paper, we analyze the RAM usage and propose power-aware page allocation policy. Especially the pages mapped into the process' address space and the buffer cache pages are considered. The relationship and interactions of these two kinds of pages are analyzed and exploited for energy saving.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1199-1202
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• 1998

4채널 입력으로부터 입력되는 오디오를 압축,복원,저장, 전송하는 ㅅ스템을 설계한다. 이러한 시스템은 보안 시스템 중에서 특정 센서로부터 alarm 신호를 디지털 데이터로 변환한 후, 압축시켜 저장하고 동시에 압축된 오디오 데이터를 비디오 데이터와 통합하여 하나의 스트림으로 만들어 통신망으로 보내주는 시스템에 적용된다. 이러한 시스템의 구조를 간단히 설명하면 아날로그 음성 신호를 디지털 음성 data로 변환하기 위해 OKI사의 MSM 7570L-91이라는 ADPCM codec을 사용하였고 ADPCMcodec을 거쳐 나온 ADPCM 데이터를 64Mbyte SDRAM에 저장하였다가 FIFO를 거쳐서 통신망으로 전송을 한다. 복원은 SDRAM에 저장된 ADPCM 데이터를 MSM 7570L-01을 거쳐 아날로그 신호로 변환한 후 엠프를 거쳐 스피커로 출력을 하게 된다.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10a
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• pp.247-248
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• 2007

• Electronics and Telecommunications Trends
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• v.15 no.6 s.66
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• pp.118-127
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• 2000

DRAM 메모리는 FPM DRAM, EDO DRAM, SDRAM, DDR/DDR II SDRAM, RDRAM, FCRAM 등의 범용 구조와 VRAM, WRAM, CDRAM, MDRAM 등의 디스플레이용 구조로 크게 나눌 수 있다. DRAM의 가장 큰 어플리케이션은 PC 부문이며, DRAM은 각 어플리케이션별 비용/성능 트레이드 오프에 따라 선호되는 구조가 달라서 당분간은 여러 구조가 공존할 것으로 보인다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.108-114
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• 1995

Recently, along wtih the advance of high-performance system, synchronous DRAM's (SDRAM's) which provide consecutive data output synchronized with an external clock signal, have been reported. However, in the conventional SDRAM's which utilize a multi-stage serial pipelined scheme, the column path is divided into multi-stages depending on CAS latency N. Thus, as the operating speed and CAS latency increase, new stages must be added, thereby causing a large area penalty due to additinal latches and I/O lines. In the proposed register-based parallel pipelined scheme, (N-1) registers are located between the read data bus line pair and the data output buffer and the coming data are sequentially stored. Since the column data path is not divided and the read data is directly transmitted to the registers, the busrt read operation can easily be achieved at higher frequencies without a large area penalty and degradation of internal timing margin. Simulation results for 0.32um-Tech. 4-Bank 64M SDRAM show good operation at 200MHz and an area increment is less than 0.1% when CAS latency N is increased from 3 to 4.. This pipelined scheme is more advantageous as the operating frequency increases.

• ETRI Journal
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• v.32 no.1
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• pp.84-92
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• 2010

This paper proposes the semaphore authority management (SAM) controller to optimize the dual-port SDRAM (DPSDRAM) in the mobile multimedia systems. Recently, the DPSDRAM with a shared bank enabling the exchange of data between two processors at high speed has been developed for mobile multimedia systems based on dual-processors. However, the latency of DPSDRAM caused by the semaphore for preventing the access contention at the shared bank slows down the data transfer rate and reduces the memory bandwidth. The methodology of SAM increases the data transfer rate by minimizing the semaphore latency. The SAM prevents the latency of reading the semaphore register of DPSDRAM, and reduces the latency of waiting for the authority of the shared bank to be changed. It also reduces the number of authority requests and the number of times authority changes. The experimental results using a 1 Gb DPSDRAM (OneDRAM) with the SAM controllers at 66 MHz show 1.6 times improvement of the data transfer rate between two processors compared with the traditional controller. In addition, the SAM shows bandwidth enhancement of up to 38% for port A and 31% for port B compared with the traditional controller.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.411-414
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• 2010

본 논문은 비디오 처리를 위한 고성능의 메모리 제어기를 설계하였다. 메모리 제어기는 arbiter에 의해 제어되며 이것은 메모리 억세스를 요구하는 모듈들의 요구 신호를 받아 데이터를 전송하는 역할을 해주게 된다. 구현된 메모리 제어기는 버스를 사용하기 위한 승인을 받기 위해서 마스터와 신호를 주고 받는 MAU블록, grant 신호를 디코딩하고 컨트롤 신호의 상태를 정의한 arbiter 블록, SDRAM의 ac parameter를 저장하고 bank의 준비 여부, read/write 가능 여부, precharge와 refresh의 가능 여부를 확인하여 system과 read/write가 준비되었다는 신호를 출력, SDRAM의 실질적인 입력신호를 생성하는 memory accelerator 블록, 생성된 입력신호를 저장하고 마스터에서 직접 write data를 입력 받는 memory I/F 블록으로 구성된다. 이 메모리 제어기는 174.28MHz의 주파수로 동작하였다. 본 설계는 VHDL을 이용하여 설계되었고, ALTERA의 Quartus II를 이용하여 합성하였다. 또한 ModelSim을 이용하여 설계된 회로를 검증하였다. 구현된 하드웨어는 StatixIII EP3SE80F1152C2 칩을 사용하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.455-462
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• 2015

H-field EMI measurements have been performed for the single-ended, the differential, and the pseudo-differential signaling on a 11" FR4 microstrip line. The pseudo-differential signaling reduces EMI by more than 10 dB compared to the single-ended signaling if the delay mismatch is lower than 5% of a period for a 3 GHz clock signal. Empirical H-field equations for both differential and single-ended signaling showed fair agreements with measurements.

• ETRI Journal
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• v.39 no.3
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• pp.428-436
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• 2017

State-of-the-art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap-around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap-round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap-around order, but the rearrangement process may increase memory latency and waste the bandwidth of on-chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap-around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.25-32
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• 2012

Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.