• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
• /
• pp.87.2-87.2
• /
• 2015

Transparent conductors are commonly used in photoelectric devices, where the electric energy converts to light energy or vice versa. Energy consumption devices, such as LEDs, Displays, Lighting devices use the electrical energy to generate light by carrier recombination. Meanwhile, solar cell is the only device to generate electric energy from the incident photon. Most photoelectric devices require a transparent electrode to pass the light in or out from a device. Beyond the passive role, transparent conductors can be employed to form Schottky junction or heterojunction to establish a rectifying current flow. Transparent conductor-embedded heterojunction device provides significant advantages of transparent electrode formation, no need for intentional doping process, and enhanced light-reactive surface area. Herein, we present versatile applications of transparent conductors, such as NiO, ZnO, ITO in photoelectric devices of solar cells and photodetectors for high-performing UV or IR detection. Moreover, we also introduce the growth of transparent ITO nanowires by sputtering methods for large scale application.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 1999년도 춘계종합학술대회
• /
• pp.415-419
• /
• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• 센서학회지
• /
• 제25권3호
• /
• pp.184-188
• /
• 2016

Highly ordered $SnO_2$ and NiO nanocolumns have been successfully achieved by glancing-angle deposition (GLAD) using an electron beam evaporator. Nanocolumnar $SnO_2$ and NiO sensors exhibited high performance owing to the porous nanostructural effect with the formation of a double Schottky junction and high surface-to-volume ratios. When all gas sensors were exposed to various gases such as $C_2H_5OH$, $C_6H_6$, and $CH_3COCH_3$, the response of the highly ordered $SnO_2$ nanocolumn were over 50 times higher than that of the $SnO_2$ thin film. This work will bring broad interest and create a strong impact in many different fields owing to its particularly simple and reliable fabrication process.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
• /
• pp.318.2-318.2
• /
• 2014

The high contact resistance is still one of the major issues to be resolved in CdS/CdTe thin film solar cells. CdTe/Metal Schottky contact induced a high contact resistance in CdS/CdTe solar cells. It has been reported that the work function of CdTe thin film is more than 5.7 eV. There has not been a suitable back contact metal, because CdTe thin film has a high work function. In a few decades, some buffer layer was reported to improve a back contact problem. Buffer layers which are Te, $Sb_2Te_3$, $Cu_2Te$, ZnTe:Cu and so on was inserted between CdTe and metal electrode. A formed buffer layers made a tunnel junction. Hole carriers which was excited in CdTe film by light absorption was transported from CdTe to back metal electrode. In this report, we reported the variation of solar cell performance with different buffer layer at the back contact of CdTe thin film solar cell.

• E2M - 전기 전자와 첨단 소재
• /
• 제8권2호
• /
• pp.176-183
• /
• 1995

The present work is concerned with the switching conduction characteristics of PI LB films in metal insulator metal sandwiches. By applying various DC voltage bias to MIM junctions, conduction characteristics of junctions can be changed between the high-voltage low-current(off) condition, the low-voltage high-current (on) condition and the medium(mid) condition. Switching conduction characteristics can be also observed in MIM junctions employing some aromatic compounds as insulators. Switching conduction characteristics is assumed to be owing to the existence of aromatic rings, space charge in films, impurities on metal-insulator interface, and difference in work functions of base and top electrodes metal. To study the conduction process of on, off, and mid conductions, we measured I-V, d$^{2}$V/d I$^{2}$-V characteristics of junctions with several different top electrodes under various temperatures. Small conductance changes of junctions can be measured by observing the second derivative, d$^{2}$V/dI$^{2}$, of I-V curve. A dynamical technique is used to get the second derivatives. That is, a finite modulation of the current is applied to the junctions and the second harmonic of the voltage is detected.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제17권2호
• /
• pp.239-244
• /
• 2017

We experimentally investigate the physical mechanism for asymmetrical degradation in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses. The transfer curves exhibit an asymmetrical negative shift after the application of gate-to-source ($V_{GS}$) and drain-to-source ($V_{DS}$) bias stresses of ($V_{GS}=24V$, $V_{DS}=15.9V$) and ($V_{GS}=22V$, $V_{DS}=20V$), but the asymmetrical degradation is more significant after the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20 V) nevertheless the vertical electric field at the source is higher under the bias stress ($V_{GS}$, $V_{DS}$) of (24 V, 15.9 V) than (22 V, 20 V). By using the modified external load resistance method, we extract the source contact resistance ($R_S$) and the voltage drop at $R_S$ ($V_{S,\;drop}$) in the fabricated a-IGZO TFT under both bias stresses. A significantly higher RS and $V_{S,\;drop}$ are extracted under the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20V) than (24 V, 15.9 V), which implies that the high horizontal electric field across the source contact due to the large voltage drop at the reverse biased Schottky junction is the dominant physical mechanism causing the asymmetrical degradation of a-IGZO TFTs under simultaneous gate and drain bias stresses.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제8권1호
• /
• pp.66-79
• /
• 2008

Several oxides have recently been reported to have resistance-switching characteristics for nonvolatile memory (NVM) applications. Both binary and ternary oxides demonstrated great potential as resistive-switching memory elements. However, the switching mechanisms have not yet been clearly understood, and the uniformity and reproducibility of devices have not been sufficient for gigabit-NVM applications. The primary requirements for oxides in memory applications are scalability, fast switching speed, good memory retention, a reasonable resistive window, and constant working voltage. In this paper, we discuss several materials that are resistive-switching elements and also focus on their switching mechanisms. We evaluated non-stoichiometric polycrystalline oxides ($Nb_2O_5$, and $ZrO_x$) and subsequently the resistive switching of $Cu_xO$ and heavily Cu-doped $MoO_x$ film for their compatibility with modem transistor-process cycles. Single-crystalline Nb-doped $SrTiO_3$ (NbSTO) was also investigated, and we found a Pt/single-crystal NbSTO Schottky junction had excellent memory characteristics. Epitaxial NbSTO film was grown on an Si substrate using conducting TiN as a buffer layer to introduce single-crystal NbSTO into the CMOS process and preserve its excellent electrical characteristics.

• 전기학회논문지
• /
• 제67권6호
• /
• pp.789-793
• /
• 2018

All transparent metal oxide photoelectric device based on $V_2O_5$ was fabricated with structure of $V_2O_5/ZnO/ITO$ by magnetron sputtering system. $V_2O_5$ was deposited by reactive sputtering system with 4 inch vanadium target (purity 99.99%). In order to achieve p-n junction, p-type $V_2O_5$ was deposited onto the n-type ZnO layer. The ITO (indium tin oxide) was applied as the electron transporting layer for effective collection of the photo-induced electrons. Electrical and optical properties were analyzed. The Mott-Schottky analysis was applied to investigate the energy band diagram through the metal oxide layers. The $V_2O_5/ZnO/ITO$ photoelectric device has a rectifying ratio of 99.25 and photoresponse ratios of 1.6, 4.88 and 2.68 under different wavelength light illumination of 455 nm, 560 nm and 740 nm. Superior optical properties were realized with the high transmittance of average 70 % for visible light range. Transparent $V_2O_5$ layer absorbs the short wavelength light efficiently while passing the visible light. This research may provide a route for all-transparent photoelectric devices based on the adoption of the emerging p-type $V_2O_5$ metal oxide layer.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.591-591
• /
• 2012

본 연구는 Transparent conducting oxide (TCO, 산화물투명전극)를 이용한 박막태양전지 효율향상에 관한 것으로, 이중의 TCO층(Double-stacked TCO layer)의 효과적인 광학 및 전기적 설계에 관한 것이다. 기존 박막 태양전지에서는 투명전극 TCO layer로서, ITO (Indium-Tin-Oxide), FTO (Fluorine- Tin-Oxide), 및 AZO(Aluminum-doped Zinc Oxide) 등을 사용해 왔다. 각 TCO layer마다 장점이 있지만 단점 또한 존재한다. ITO의 경우 높은 전기적 특성을 가지는 반면 수소 플라즈마에 취약하고 기계적 강도에 취약해 ITO 단일층만으로 박막 태양전지에 적용하는 것에 제한을 받는다. 한편, AZO의 경우 전기적 특성도 우수할 뿐만 아니라 수소 플라즈마에도 내구성이 강한 장점이 있지만, 일함수가 p형 반도체보다 낮아 Schottky junction이 되어, 높은 전위장벽이 형성된다. 이는 정공의 이동을 방해하고, 정공의 축적이 일어나서 순방향 전압을 인가할 때 많은 전류의 감소를 가져온다. 또한, AZO와 p형 반도체 사이의 높은 직렬저항으로 인해 광전압(Voc, Open circuit voltage)와 충실률 (FF, Fill factor)가 떨어진다는 단점이 있다. 본 실험에서는 ITO/AZO 2중구조의 TCO층을 적용하여 상기의 문제점을 해결하고자 한다. 이중 구조 TCO층은 Magnetron sputter system을 이용하여, 단계적으로 증착되었다. 빛이 입사하는 유리에 ITO를 제1전도층으로 증착하였는데, ITO는 입사광의 투과도와 전기전도성이 우수하다. 제2전도층으로는 AZO층을 이용하였으며, 실리콘 반도체층과 접하게 된다. AZO는 실리콘 증착시 발생하는 수소 플라즈마에 안정적이고, 물리적 강도 또한 우수한 장점이 있다. 이중 구조층위에 실리콘 광흡수층(Si absorber)을 증착하였으며, pin 구조를 가진다. 기존, 단일막 TCO층과 2중구조 TCO층을 이용하여, 실리콘 박막 태양전지를 구성하였다. 이때, ITO/AZO의 2중구조를 적용하였을 때 태양 전지 특성이 크게 향상된 결과를 얻을 수가 있었다. 특히, 전류밀도의 경우 ITO, FTO, AZO 각각 14.5 mA/cm2, 11.2 mA/cm2, 8.18 mA/cm2를 나타낸 반면 ITO/AZO 2중구조의 경우 약 17mA/cm2 로 크게 향상 되었고, 태양전지 변환 효율도 각각 7.5%, 6.9%, 4%에서 ITO/AZO 2중 구조의 경우 8.05%로 크게 향상되었다. 본 발표에서는 2중구조 TCO를 이용한 현공정에 적용 가능한 박막태양전지 효율향상 기법에 대해 논의하고자 한다.