• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.4
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• pp.119-127
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• 2021

The aim of this paper is to propose a less conservative stabilization condition for leader-following sampled-data control of wheeled mobile robot (WMR) systems by using a clock-dependent Lyapunov function (CDLF) with looped functionals. In the leader-following WMR system, the state and input of the leader robot are measured by digital devices mounted on the following robot, and they are utilized to construct the sampled-data controller of the following robot. To design the sampled-data controller, a stabilization condition is derived by using the CDLF with looped functionals, and formulated in terms of sum of squares (SOS). The considered Lyapunov function is a polynomial form with respect to the clock related to the transmitted sampling instants. As the degree of the Lyapunov function increases, the stabilization condition becomes less conservative. This ensures that the designed controller is able to stabilize the system with a larger maximum sampling interval. The simulation results are provided to demonstrate the effectiveness of the proposed method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.680-687
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• 2018

Borehole radar is a radar used for underground resources and geological exploration purposes. It needs a high-speed sampler to transmit electromagnetic waves with a pulse width of several ns and to receive reflected waves of several tens to several hundreds of MHz reflected from the object to be surveyed. ETS (Equivalent-Time Sampling), which can achieve sampling performance of several GHz with a sampling frequency of several tens of MHz, is suitable for use as a sampler of a borehole radar receiver. In this paper, we propose a method to control the sampling clock delay, which is the most important factor in ETS sampler design, using four clocks with phase difference of $90^{\circ}$ for one clock source. The proposed method can reduce the time required to acquire the data within the set interval by 1/25 than the conventional method using the delay generator. When the implemented sampler is applied to the receiver of existing borehole radar, it is possible to accumulate 58 additional times due to the shortened sampling time. In addition, by using one delay control logic compared with the conventional method using several sampling clock delay control logic in order to satisfy the target sampling range, it is possible to omit the correction process which was necessary in the past. As a result, the structure of the system can be simplified and a uniform sampler can be realized.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• Ocean and Polar Research
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• v.22 no.2
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• pp.57-67
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• 2000

Time-selective self-triggering water sampler, AUTTLE developed by Jin et al. (1999) has been improved in order to prevent pre-deposition of suspended sediments (SS) before sampling. By using two solenoids, the improved sampler is able to be moored or deployed with inclination. Its position is changed to horizontal position by activating the first solenoid, and then the endcaps of the sampling bottle are closed by the second solenoid that is driven three times to minimize possible failure of sampling. An external control unit for setting sampling time has been also constructed. Additionally, the electric circuit housing of the sampler has been modified to be detached from the sampling bottle when operating manually. Its performance has been confirmed through flume tests and a field experiment. It will serve as a valuable tool in the various fields of oceanography and environmental engineering, especially where seawater sampling synchronized at several sites and/or the information in storm period is important.

• ETRI Journal
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• v.28 no.1
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• pp.31-44
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• 2006

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.33.3-33
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• 2002

Pseudolite (PL) is a kind of signal generator, which transmits GPS-like signal at the ground. However our own made PL is different from a GPS satellite in clock accuracy. GPS satellites are synchronized by use of high precision atomic clocks. But because our PLs use low cost temperature controlled oscillators (TCXO), so it is very difficult to synchronize them. Hence, we should install reference station and use Differential GPS (DGPS) algorithm to calculate user position. By use of this method, we already developed indoor navigation system a few years ago. We named it as 'Asynchronous Pseudolite Indoor Navigation System'. However, this system requires that sampling times of all the receivers...

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1004-1011
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• 2005

In OFDM (Orthogonal Frequency Division Multiplexing) system, sampling frequency offset causes performance degradation due to increase of ICI. Sampling frequency offset can be generally estimated by correlation of the pilot signal or the known pattern within two contiguous OFDM symbol however, this method has the throughput degradation and the difficulty in applying to various OFDM systems. In this paper, we propose a new algorithm for sampling frequency offset estimation which can solve aforementioned issues. The proposed algorithm uses a single OFDM symbol to prevent throughput degradation and to apply to various OFDM-based communication systems flexibly Also, the proposed algorithm can enhance reliability by observing more number of correlations compared to the established algorithm in frequency domain. Extensive computer simulation shows that the proposed algorithm can improve the system performance in various channel conditions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1242-1249
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• 2012

This paper proposes a metastability-free synchronization method and a mesochronous synchronizer for NoC. It uses the clock transmitted from TX as a strobe and solves the metastability problem by selecting one of rising or falling clock edge depending on the sampling value in RX when the phase difference between clocks is under a metastability window. The logic simulation results show that it works without metastability under $0^{\circ}{\sim}360^{\circ}$ phase difference in the synchronizer that a fault is inserted. The mesochronous synchronizer has a simple control logic and is suitable for NoC.