• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
• /
• pp.201-204
• /
• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values, So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of $I_D-V_D$ $I_D-V_G$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11a
• /
• pp.201-204
• /
• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values. So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of I$_{D}$-V$_{D}$, I$_{D}$-V$_{G}$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.ristics.

• Journal of the Korean Vacuum Society
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• v.3 no.3
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• pp.341-345
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• 1994

As+ 와 P+ 이온들이 주입된 실리콘에서 주입 이온들의 확산 및 실리콘의 재결정화에 열처리가 미치는 영향에 대해서 조사하였다, 여기서 이온 주입량은 실리콘 표면영역을 비정질화하기에 충분한 양 이었다. 이온 주입 시실리콘 내부에 생성된 손상들을 제거하기 위해 온도와 시간을 변화시켜 가며 시편 을 전기로 속에서 열처리하였다. 그러나 이때 야기된 도우펀트들의 과도적인 확산에 의해서 접합깊이는 예측한 것보다 더욱 깊은 곳에서 나타나다. 이러한 과도적인 확산은 주로 이온 주입으로 인해 야기된 시편들이 손상들을 제거하기 위한 열처리 과정동안 일어난 것으로 생각된다. 이것은 SIMS와 SUPREM IV simulation 에 의해서 확인할 수 가 있었다. As+ 와 P+ 이온이 주입된 실리콘의 결정성 회복을 Raman 분광법을 이용하여 조사하였다.