• Proceedings of the Korea Information Processing Society Conference
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• 2020.11a
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• pp.12-15
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• 2020

Data access characteristics can directly affect the efficiency of the system execution. This research is to design an accurate predictor by using historical memory access information, where highly accessible data can be migrated from low-speed storage (SSD/HHD) to high-speed memory (Memory/CPU Cache) in advance, thereby reducing data access latency and further improving overall performance. For this goal, we design a locally weighted linear regression prefetch scheme to cope with irregular access patterns in large graph processing applications for a DARM-PCM hybrid memory structure. By analyzing the testing result, the appropriate structural parameters can be selected, which greatly improves the cache prefetching performance, resulting in overall performance improvement.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.23-31
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• 2011

Recently, Solid state disk is mainly used because this device has lower power consumption as well as higher response time. But it features higher price and lower performance at delete and write operations compared with HDD. To compensate this defect, Hybrid hard disk with internal non-volatile flash memory was issued. This NVCache is used as a kind of cache for disk blocks. In this paper, an I/O scheme for H-HDD is proposed for improving low power consumption as well as response time. Our method is to use this NVCache as read cache mainly and write cache when write requests are concentrated. In read cache operation, disk blocks with higher priority determined on basis of time as well as spatial localities are prefetched, which can improve response time. The write operation is conducted only at write peak time as disk spindle up costs higher battery power as well as response time. Experiments results show that the suggested method can improve response time of H-HDD and lower the power consumption.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.913-917
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• 2009

Flash memories have asymmetric I/O costs for read and write in terms of latency and energy consumption. However, the ratio of these costs is dependent on the type of storage. Moreover, it is becoming more common to use two flash memories on a system as an internal memory and an external memory card. For this reason, buffer cache replacement algorithms should consider I/O costs of device as well as possibility of reference. This paper presents WWCLOCK(Write-Weighted CLOCK) algorithm which directly uses I/O costs of devices along with recency and frequency of cache blocks to selecting a victim to evict from the buffer cache. WWCLOCK can be used for wide range of storage devices with different I/O cost and for systems that are using two or more memory devices at the same time. In addition to this, it has low time and space complexity comparable to CLOCK algorithm. Trace-driven simulations show that the proposed algorithm reduces the total I/O time compared with LRU by 36.2% on average.

• Proceedings of the Korean Society of Computer Information Conference
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• 2020.01a
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• pp.1-2
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• 2020

응용프로그램의 응답성을 향상시키기 위해서는 저장장치 시스템의 데이터 처리 능력이 중요하다. 한편, 차세대 메모리(NVDIMM)는 DRAM과 SSD 중간 정도의 성능 특성과 저장 용량을 갖는다. NVDIMM을 저장장치의 캐시로 사용함으로써 메모리와 저장장치의 격차는 많이 줄게 된다. 본 논문에서는 경량의 재사용 거리 측정 기법을 이용하여 효율적으로 디스크를 캐싱하는 기법을 제안한다. 제안 기법은 경량의 재사용 거리 측정 기법을 바탕으로 계산된 CFD(Computational Fluid Dynamics)값에 따라 디스크 캐시에 해당 데이터 적재 여부를 결정한다. 결과적으로 제안 기법을 적용한 디스크 캐시를 운용함에 따라 캐시의 히트율을 향상시켰다.

• The KIPS Transactions:PartD
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• v.19D no.2
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• pp.161-186
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• 2012

Recently, the flash memory consistently increases the storage capacity while the price of the memory is being cheap. This makes the mass storage SSD(Solid State Drive) popular. The flash memory, however, has a lot of defects. In order that these defects should be complimented, it is needed to use the FTL(Flash Translation Layer) as a special layer. To operate restrictions of the hardware efficiently, the FTL that is essential to work plays a role of transferring from the logical sector number of file systems to the physical sector number of the flash memory. Especially, the poor performance is attributed to Erase-Before-Write among the flash memory's restrictions, and even if there are lots of studies based on the log block, a few problems still exists in order for the mass storage flash memory to be operated. If the FAST based on Log Block-Based Flash often is generated in the wide locality causing the random writing, the merge operation will be occur as the sectors is not used in the data block. In other words, the block thrashing which is not effective occurs and then, the flash memory's performance get worse. If the log-block makes the overwriting caused, the log-block is executed like a cache and this technique contributes to developing the flash memory performance improvement. This study for the improvement of the random writing demonstrates that the log block is operated like not only the cache but also the entire flash memory so that the merge operation and the erase operation are diminished as there are a distinct mapping table called as the offset mapping table for the operation. The new FTL is to be defined as the XAST(extensively-Associative Sector Translation). The XAST manages the offset mapping table with efficiency based on the spatial locality and temporal locality.