• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.5
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• pp.1143-1151
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• 2015

Extensible Storage Engine (ESE) database is a database developed by Microsoft. This database is used in web browser like Internet Explorer, Spartan and in Windows system with Windows Search, System Resource Usage Monitor. Previous ESE database viewer can display an incorrect result and can't read the file depending on collected environment and status of files. And the deleted record recovery tool is limited to some program and cannot recover all tables. This paper suggests the universal recovery method for deleted records and presents the experimental results through development of tool.

• International Journal of Aeronautical and Space Sciences
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• v.18 no.4
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• pp.675-687
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• 2017

In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.413-420
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• 2006

In this thesis, a RFID baseband system is implemented based on the international standard ISO/IEC 18000-6 Type-B using FPCA, and also anti-collision algorithm is implemented to improve the system performance. We compares the performance of the proposed anti-collision algorithm with that binary tree algorithm and bit-by-bit algorithm, and also validated analytic results using OPNET simulation. The proposed algorithm for Type-B transmission protocol and collision prohibition was designed using ISE7.1i which is a FPGA design-tool of Xilinx and implemented with Spartan2 chip which is a FPGA device.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.10
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• pp.831-835
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• 2020

By automatically generating HDL codes from C/C++ source codes, HLS makes it possible to shorten FPGA system developing period through easy timing control and structure change. We designed LDPC encoder for telemetry standard 106-17 with Xilinx Vivado HLS and showed hardware structure can be easily adapted for different purposes through minor C code modification. Synthesis results targeting Spartan-7 xc7s100 device are presented for throughput and hardware complexity comparison.

• The Journal of the Korea Contents Association
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• v.13 no.4
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• pp.44-52
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• 2013

The SIFT algorithm is being actively researched for various image processing applications including video surveillance and autonomous vehicle navigation. The computation of sin/cos function is the most cost part needed in whole computational complexity and time for SIFT descriptor. In this paper, we implement a hardware to sin/cos function of descriptor on sift feature detection algorithm. The proposed Sin/Cosine processor is coded in Verilog and synthesized and simulated using Xilinx ISE 9.2i. The processor is mapped onto the device Spartan 2E (XC2S200E-PQ208-6). It consumes 149 slices, 233 LUTs and attains a maximum operation frequency of 60.01 MHz. As compared with the software realization, our FPGA circuit can achieve the speed improvement by 40 times in average.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.833-835
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• 2010

The SPARTAN-3E development kit is equipped with an FPGA which holds 500 thousand logic gates and a bus system platform using MicroBlaze microprocessor system. This kind of embedded systems can be used to gather information from sensor nodes and send over to the main server periodically through the network gateway, using the microprocessor-based embedded system, so that edlers living alone under sensor coverage can send their moving information and can be applied to get help in the event of emergency situations. In this paper, we designed a simple embedded system based on a CPU and flash memories using such FPGAs which can be used to monitor those elderlies living alone. The developed hardware system can be directly combined with the web-based elders-living-alone monitoring system, making the system more efficient.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.584-586
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• 2017

In this paper we provide a unified crypto core that integrates lightweight symmetric cryptography and authentication. The crypto core implements a unified 128 bit key architecture of PRESENT encryption algorithm and a new lightweight encryption algorithm. The crypto core also consist of an authentication unit which neglects the use of hashing algorithms. Four algorithms are used for authentication which come from the Hopper-Blum (HB) and Hopper-Blum-Munilla-Penado (HB-MP) family of lightweight authentication algorithms: HB, HB+, HB-MP and HB-MP+. A unified architecture of these algorithms is implemented in this paper. The unified cryptosystem is designed using Verilog HDL, simulated with Modelsim SE and synthesized with Xilinx Design Suite 14.3. The crypto core synthesized to 1130 slices at 189Mhz frequency on Spartan6 FPGA device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.652-654
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• 2016

This paper shows the Design and implementation of sinusoidal BLDC motor drive logic using SVPWM method with FPGA. Sinusoidal BLDC motor driver logic consists of sine-wave PWM generator, dead-time and lead angle control logic. PWM generator logic is designed using SVPWM method for increase of 15.5% linear domain than general sine-wave PWM. This logic is verified and implemented using Spartan-6 FPGA Board. Test results show that THD(Total Harmonic Distortion) of motor-driving current is 19.2% and rotor position resolution is 1.6 degree.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.108-112
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• 2016

화학, 물리. 재료, 공학 등 여러 분야에서 계산의 중요성이 증가함에 따라 대학 학부수업에서 계산을 가르치는 학교들이 늘어나고 있다. 수업에서 진행되는 tutorial 의 경우, Gaussian, Spartan, Hyperchem 과 같은 상업용 프로그램을 이용하여 간단한 이론들을 시뮬레이션 하는 방식으로 진행된다. 이번 연구에서는 EDISON 프로그램을 활용하여 계산화학을 처음 접하는 학생들을 위한 tutorial 을 개발하였다. EDISON S/W 를 기반으로한 이 tutorial 이 교과서에서 배우던 개념들을 이해하는데 도움이 되며, 실제 수업시간에 사용될 수 있음을 보여주고자 한다.

• Proceedings of the KAIS Fall Conference
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• 2003.06a
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• pp.250-252
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• 2003

본 논문에서는 콘벌루션 부호를 사용한 대역확산 방식의 디지틀 통신모뎀을 FPGA를 이용하여 설계 및 검증을 하였다. 대역확산 방식에서의 콘벌루tus부호기(K=3, R=1/2), PN code(128chip) generator와 비터비 디코더를 Xilinx사의 FPGA 디자인 툴인 Xilinx Foundations3.1을 사용하여 VHDL simulation과 timing simulation을 수행하였고, FPGA 회로설계 검증 장비인 EDA-Lab 3000 장비를 사용하여 Xilinx사의 SPARTAN2 2S100PQ208칩에 configuration 한 후 Agilent사의 1681A logic analyzer를 사용하여 설계된 회로의 동작을 검증하였다.