• Title/Summary/Keyword: SMD chip

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Automatic Classification of SMD Packages using Neural Network (신경회로망을 이용한 SMD 패키지의 자동 분류)

  • Youn, SeungGeun;Lee, Youn Ae;Park, Tae Hyung
    • Journal of Institute of Control, Robotics and Systems
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    • v.21 no.3
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    • pp.276-282
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    • 2015
  • This paper proposes a SMD (surface mounting device) classification method for the PCB assembly inspection machines. The package types of SMD components should be classified to create the job program of the inspection machine. In order to reduce the creation time of job program, we developed the automatic classification algorithm for the SMD packages. We identified the chip-type packages by color and edge distribution of the images. The input images are transformed into the HSI color model, and the binarized histroms are extracted for H and S spaces. Also the edges are extracted from the binarized image, and quantized histograms are obtained for horizontal and vertical direction. The neural network is then applied to classify the package types from the histogram inputs. The experimental results are presented to verify the usefulness of the proposed method.

Frequency Characteristics for Micro-scale SMD RE Chip Inductors of Solenoid-Type (Solenoid 형태의 초소형 SMD RF 칩 인덕터에 대한 주파수 특성)

  • Kim, Jae-Wook
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.8 no.3
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    • pp.454-459
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    • 2007
  • In this work, micro-scale, high-performance solenoid-type RF chip inductors utilizing amorphous $Al_2O_3$ core material were investigated. The size of the chip inductors was $0.86{\times}0.46{\times}0.45mm^3$ and copper(Cu) wire with $27{\mu}m$ diameter was used as the coil. High frequency characteristics of the inductance(L), quality factor(Q), impedance(Z), and equivalent circuit parameters of the RE chip inductors were measured and analyzed using an RF impedance/material analyzer(HP4291B with HP16193A test fixture). It was observed that the RF chip inductors with the number of turns of 9 to 12 have the inductance of 21 to 34nH and exhibit the self-resonant frequency(SRF) of 5.7 to 3.7GHz. The SRF of inductors decreases with increasing the inductance and inductors have the quality factor of 38 to 49 in the frequency range of 900MHz to 1,7GHz.

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A high-resolution synchronous mirror delay using successive approximation register (연속 근사 레지스터를 이용한 고정밀도 동기 미러 지연 소자)

  • 성기혁;김이섭
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.10
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    • pp.63-68
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    • 2004
  • A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the infernal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the SMD. Fine locking is achieved by the successive approximation register-controlled DLL. The total locking time is 10 clock cycles. Simulation results show that the proposed SMD operates with 50psec clock skew at 182MHz and consumes 17.5mW at 3.3V supply voltage in a 0.35 um 1-poly 4-metal CMOS technology.

Thermal Cycling Analysis of Flip-Chip BGA Solder Joints (플립 칩 BGA 솔더 접합부의 열사이클링 해석)

  • 유정희;김경섭
    • Journal of the Microelectronics and Packaging Society
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    • v.10 no.1
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    • pp.45-50
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    • 2003
  • Global full 3D finite element analysis fatigue models are constructed for flip-chip BGA on system board to predict the creep fatigue life of solder joints during the thermal cycling test. The fatigue model applied is based on Darveaux's empirical equation approach with non-linear viscoplastic analysis of solder joints. The creep life was estimated the creep life as the variations of the four kinds of thermal cycling test conditions, pad structure, composition and size of solder ball. The shortest fatigue life was obtained at the thermal cycling test condition from $-65^{\circ}C$ to $150^{\circ}C$. It was increased about 3.5 times in comparison with that from $0^{\circ}C$ to $100^{\circ}C$. At the same conditions, the fatigue life of SMD structure as the change of pad structure increased about 5.7% as compared with NSMD structure. Consequently, it was confirmed that the fatigue life became short as the creep strain energy density increased in solder joint.

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The analysis and design of X-ray cross sectional imaging system for PCB solder joint inspection (PCB 납땜 검사를 위한 X선 단층 영상 시스템의 해석 및 설계)

  • 노영준;강성택;김형철;김성권
    • 제어로봇시스템학회:학술대회논문집
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    • 1996.10b
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    • pp.109-112
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    • 1996
  • The more integrated and smaller SMD are needed, new solder joints packaging technologies are developed in these days such as BGA(Ball Grid Array), Flip Chip, J-lead etc. But, it's unable to inspect solder joints in those devices by visual inspection methods, because they are hided by it's packages. To inspect those new SMD packages, an X-ray system for acquiring a cross-sectional image of a arbitrary plane is necessary. In this paper, an analysis for designing X-ray cross sectional imaging system is presented including the way for correcting the distortion of image intensifier. And we show computer simulation of that system with a simple PCB model to show it's usefulness in applying PCB solder joint inspection.

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The surface mounting technology to prevent improper fine chip insertions by using fiber sensors (Fiber sensor를 이용한 미소칩 미삽 방지 표면실장기술)

  • Kim, Young-Min;Kim, Hyun-Jong;Um, Sun-Chon;Kong, Heon-Tag;Kim, Chi-Su
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.9
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    • pp.4138-4146
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    • 2011
  • In surface mount technology, with cellular phones and flat panel displays shrinking in size, the electric goods for making these things are getting smaller as well. Therefore, the technology of mounting components such as 0402 and 0603 Chip is on the rise. The chip mount manufacturing companies have studied the mount technology to prevent the missing insertions or improper insertion. This study suggests arranging the mechanical structure by using fiber sensors to eliminate missing insertions or improper insertions and developing the technology for upgrading system algorithms.

Thermal Cycling Fatigue Analysis of Flip-Chip BGA Solder Joints (플립 칩 BGA 솔더접합부의 열사이클링 피로해석)

  • 김경섭;유정희;김남훈;장의구;임희철
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.11a
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    • pp.27-32
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    • 2002
  • In this paper, global full 3D finite element analysis fatigue models are constructed for flip-chip BGA on board to predict the creep fatigue life of solder joints during the thermal cycling test. The fatigue model applied is based on Darveaux's empirical equation approach with non-linear viscoplastic analysis of solder joints. It was estimated by the creep life as the variations of the four kinds of thermal cycling test conditions, pad structure, composition and size of solder ball. The shortest fatigue life of results was obtained at the thermal cycling testing condition of -65℃ ∼ 150℃. It was increased about 3.5 times in comparison with that of 0℃ ∼ 100℃. As the change of pad structure at the same other conditions, the fatigue life of SMD structure increased about 5.7% as compared with NSMD structure. Consequently, it was confirmed that the fatigue life became short as the creep strain energy density increased in solder joint.

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Manufacture and Characteristic of Surface Mounted Device Type Fast Recovery Diode with Ceramic Package (세라믹 패키지를 이용한 표면 실장형 다이오드의 제작과 특성 평가)

  • Chun, Myoung-Pyo;Cho, Sang-Hyeok;Cho, Jeong-Ho;Kim, Byung-Ik;Yu, In-Ki
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.11a
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    • pp.221-221
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    • 2006
  • The SMD type P-N junction diode with ceramic package for diode case were fabricated. It was made this diode with simple process from $Al_2O_3$ ceramic chip, solder preform, diode chip, coating reagent and conductive paste for chip terrmination. Its merit is small size, easy manufacture. fast cooling with ceramic case. The electric characteristics of the diode such as reverse recovery time, breakdown voltage, forward voltage, and leakage current were 5 28ns, 1322V, 1.08V, $0.45{\mu}A$.

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A Development of Jig Circuit for Performance Evaluation of an Oscillator (발진기의 성능평가를 위한 지그 회로의 개발)

  • Lin, Chi-Ho;Yoon, Dal-Hwan
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.11
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    • pp.95-101
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    • 2008
  • We have used diversely the multilayer ceramic oscillator of the SMD(Surface Mounted Device) package technology that connects the crystal with the chip package. Such an oscillator occurs a stray inductance and a parasitic capacitance by the length and inner pattern. And it has been happened an amplitude attenuation and signal loss due to the reflection of power source and noise component. So we don't evaluate the precise performance of the oscillator for these factors. In this paper we have developed the Jig system to evaluate the performance of the oscillator. Through this system, we will expect an advanced performance of the oscillator and redesign an oscillator of the low jitter characteristics and low phase noise.