• 제목/요약/키워드: SMD chip

검색결과 30건 처리시간 0.022초

Varistor의 ALT(Accelerated Life Testing) 설계 및 주 고장모드 분석 (A Study for Accelerated Life Testing and Failure Analysis of Chip Varistor)

  • 장우성;이준혁;이관훈;오영환
    • 한국신뢰성학회지:신뢰성응용연구
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    • 제5권2호
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    • pp.221-239
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    • 2005
  • General chip SMD parts(chip resistance, chip capacitor, chip varistor etc.) are very wide used electronics parts for IT units. But, failure modes are indistinct for these chip parts. In factory and field the failure modes are recognized to accidental failure mode caused by potential defect. In this paper used chip varistor ALT(Accelerate Life Test) test for verify general failure modes in chip SMD parts. Also the results are useful for general chip SMD ALT tests.

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Varistor 의 ALT(Accelerated Life Testing) 설계 및 주 고장모드 분석 (A Study for Accelerated Life Testing and Failure Analysis of Chip Varistor)

  • 장우성;이준혁;이관훈;오영환
    • 한국신뢰성학회:학술대회논문집
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    • 한국신뢰성학회 2005년도 학술발표대회 논문집
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    • pp.51-67
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    • 2005
  • General chip SMD parts(chip resistance, chip capacitor, chip varistor etc.) are very wide sed electronics parts for IT units. But, failure modes are indistinct for these chip parts. In factory and field the failure modes are recognized to accidental failure mope caused by potential defect. In this paper used chip varistor ALT(Accelerate Life Test) test for verify general failure modes in chip SMD parts. Also the results are useful for general chip SMD ALT tests.

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초소형 세라믹 칩 안테나 (SMD형) 개발 (Development of ultra small chip ceramic antenna (SMD Type))

  • 이현주;정은희;오용부;이호준;윤종남;류영대;김종규
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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    • pp.131-135
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    • 2002
  • 본 연구에서는 개인 통신기의 핵심부품인 초소형 세라믹 칩 안테나 (SMD형) 개발의 무선회로 설계 기술, 초소형 설계기술, 표면실장기술, 소형화 SMD기술, Test기술 및 설계기반 마련 및 대외 경쟁력 있는 초소형 세라믹 칩 안테나 (SMD형) 개발의 초소형화 기술을 확보하였다. 중심주파수는 2442.5MHz(Type), 반사손실은 -l0dB이하, 정재파비는 2max, xy의 최대 이득은 -2dB 이상, size는 0.05ccmax이다.

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칩마운터의 진동 해석 및 실험 분석 (Vibration Analysis and Experiments of a Chip Mounting Device)

  • 고병식;이승엽
    • 한국소음진동공학회:학술대회논문집
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    • 한국소음진동공학회 2002년도 춘계학술대회논문집
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    • pp.1039-1042
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    • 2002
  • SMD(Surface Mounting Device) which mounts electronic components as IC-Chips on PCB automatically, produces a large dynamic force and vibration. The unwanted vibrations in SMD degrade the performance of the precision device and it is the major obstacle to limit its speed for mounting. This study investigated the vibration analysis of a typical SMD to predict the natural frequencies and mode shapes. To validate the finite element analysis of SMD, the FE result was compared with that of ODS measurements. It was shown that the predicted results were well correlated with the experimental modal parameters.

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A FEEDER CONTROL FOR THE SMT MOUNTER USING LON CHIP

  • Lim Eung-Kyu;Rho Sung-Chan;Kim Yoon-Ho
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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    • pp.121-125
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    • 2001
  • SMD mounter is necessary in PCB assembling line. To feed SMD components to the mounter, high performance feeders are needed. Until now, mechanical air feeders have been mainly used. However, in these days, electrical feeders with network are developed. There are many kinds of feeders with various control techniques. In this paper, a feeder with BLDC motor and LON chip is designed and implemented. And, the experimental results are presented.

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지연단을 줄인 SMD 구조의 DCC를 가지는 DLL 설계 (DLL Design of SMD Structure with DCC using Reduced Delay Lines)

  • 홍석용;조성익;신홍규
    • 전기학회논문지
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    • 제56권6호
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    • pp.1133-1138
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    • 2007
  • DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

SMD 솔레노이드 형태의 RF 칩 인덕터의 최적 구조 도출 (Optimum Structure Design of SMD Solenoid Type RF Chip Inductor)

  • 김재욱
    • 한국산학기술학회:학술대회논문집
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    • 한국산학기술학회 2010년도 춘계학술발표논문집 1부
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    • pp.124-127
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    • 2010
  • 본 논문에서는 소형 SMD 솔레노이드 형태의 RF 칩 인덕터의 최적 구조를 도출하였다. $1.0\times0.5\times0.5mm^3$ 크기의 96% $Al_2O_3$ 코아는 $40{\mu}m$ 직경의 구리 코일을 4회 권선하여 8.57nH의 인덕턴스, 37.6의 품질계수와 6.05GHz의 SRF를 가진다. $40{\mu}m$ 직경의 구리 코일을 0.35mm 솔레노이드 길이로 중앙에 6회 권선하였을 경우가 250MHz11.2nH의 인덕턴스, 29.8의 품질계수와 5.6GHz의 SRF로 가장 우수하였다.

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LON CHIP을 이용한 SMT MOUNTER의 FEEDER CONTROL (A USING LON CHIP FEEDER CONTROL FOR THE SMT MOUNTER)

  • 임응규;노성찬;김윤호
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2001년도 전력전자학술대회 논문집
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    • pp.167-171
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    • 2001
  • In PCB assembling line, it needs SMD mounter. In this paper, the feeder of the SMD mounter, which carry component to the mounter is designed. Up to now, mechanical air feeder is mainly used. But in these days, it is developed to the electrical feeder with network. There are many kind of feeders with various control technique. In this paper, the feeder with BLDC motor and LON chip is designed and implemented. Then the experimental results are presented.

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PCB에 장착된 SMD 의 부분영상을 이용한 리드의 최대 벗어난 양의 측정 (Measurement of maximum deviation of leads using partial image of SMD mounted on PCB)

  • 신동원;유준호
    • 제어로봇시스템학회논문지
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    • 제5권6호
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    • pp.698-704
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    • 1999
  • There are several types of defects of SMDs mounted on PCB, that is, missing components, misalignment, wrong parts and poor solder joints. This research study mainly focuses on measuring of deviation of SMD leads using the partial image of component, not using the full image. This processing based on the partial image has the advantage of the reduction in calculation time compared to the full image. Since position of lead is calculated with respect of the reduction in calculation time compared to the full image. Since position of lead is calculated with respect to pad, the accuracy of the system is not dependent on percise positioning stage. The grabbed image of gray scale is converted into binary format using a cutomatic threshold. After small fragments in the image is removed by a series of morphology operations such as opening and closing, the centroids of PCB pads and SMD leads is obtained together with labeling of blobs. Translational shift and rotationial angle of SMD are succedingly estimated using above information and chip data. The expression that can calculate the maximum deviation of leads with respect to PCB pads has been derived, and inferior mounting of SMD is judged by a given criterion. Some experiments have been executed to verify this measuring scheme.

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