• 제목/요약/키워드: SDRAM bus interface channel

검색결과 2건 처리시간 0.016초

High-Speed Signaling in SDARM Bus Interface Channels : Review

  • Park, Hong-June;Sohn, Young-Soo;Park, Jin-Seok;Bae, Seung-Jun;Park, Seok-Woo
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • 제1권1호
    • /
    • pp.50-69
    • /
    • 2001
  • Three kinds of high-speed signaling methods for synchronous DRAM (SDRAM) bus interface channels (PC-133, Direct-Rambus, and SSTL-2) were analyzed in terms of the timing budget and the physical transmission characteristics. To analyze the SDRAM bus interface channels, loss mechanisms and the effective characteristic impedance method were reviewed and the ABCD matrix method was proposed as an analytic and yet accurate method. SPICE simulations were done to get the AC responses and the eye patterns of the three SDRAM bus interface channels for performance comparisons. Recent progress and future trend for SDRAM bus interface standards were reviewed.

  • PDF

적외선검출기 READOUT CONTROLLER 개발 (DEVELOPMENT OF THE READOUT CONTROLLER FOR INFRARED ARRAY)

  • 조승현;진호;남욱원;차상목;이성호;육인수;박영식;박수종;한원용;김성수
    • 천문학논총
    • /
    • 제21권2호
    • /
    • pp.67-74
    • /
    • 2006
  • We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).