• 한국가구학회지
• /
• 제27권4호
• /
• pp.325-334
• /
• 2016

This study explores developing a large round table with Bosang flower pattern for a contemporary meeting room made by a cabinet maker, Kim Byeung-soo, who has built the traditional Korean furniture in Korean Western Gyeongnam Province since after his elementary school. He uses the post finger joint from one of the middle level of his education process based on the traditional Korean technique, develops it into flower stem joint, and adds flower patterns' carving decoration called Bosang flower patterns. Hence, the table makes the table be strong, useful, and beautiful. Therefore, the modernized round table will be able to make the people access more easily and to make more demand on the traditional Korean furniture and the adopted furniture than ever.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
• /
• pp.861-864
• /
• 2009

The authors have developed the display system which can be viewed from any direction. In this paper, we propose an omni-directional 3D display system for cooperative activity on a round table.

• 한국컴퓨터정보학회논문지
• /
• 제22권5호
• /
• pp.1-9
• /
• 2017

Recently, flash memory has been in a great demand from embedded system sectors for storage devices. However, program/erase (P/E) cycles per block are limited on flash memory. For the limited number of P/E cycles, many wear leveling techniques are studied. They prolonged the life time of flash memory using information tables. As one of the techniques, block erase table (BET) method using a bit array table was studied for embedded devices. However, it has a disadvantage in that performance of wear leveling is sharply low, when the consumption of memory is reduced. To solve this problem, we propose a novel wear leveling technique using Sampling-based Block Erase Table (SBET). SBET relates one bit of the bit array table to each block by using exclusive OR operation with round robin function. Accordingly, SBET enhances accuracy of cold block information and can prevent to decrease the performance of wear leveling. In our experiment, SBET prolongs life time of flash memory by up to 88%, compared with previous techniques which use a bit array table.

• 월간경쟁저널
• /
• 127호
• /
• pp.20-28
• /
• 2006

지난 6월 6일부터 9일까지 프랑스 파리에서 열린 OECD 경쟁정책위원회에서는 단독기업의 행위인 시장지배적 사업자의 지위 남용에 대한 round table 회의가 열렸다. 라운드 테이블(round table) 회의는 6월 7일 8일 두 차례에 걸쳐 개최되었는데, 7일에는 시장지배력의 정의 및 입증에 대해서, 그리고 8일에는 시장지배력의 남용행위에 대한 제재수단에 대해서는 논의가 있었다. 공정거래위원회에서 시장지배적 지위 남용을 담당하고 있는 필자는 동 회의에 참석하여 우리의 경험을 애기하고 다른 나라의 경험을 들을 수 있는 유익한 기회를 가졌었다. 여기서는 당시에 논의되었던 내용들을 정리하고 정책적 시사점을 도출하여 보고자 한다.

• 한국식생활문화학회지
• /
• 제6권1호
• /
• pp.21-29
• /
• 1991

To analyze tableware in wedding ceremonies of royal prince(1744, 1819) of Chosun Dynasty, the author studied the historic book-Gare Dogam Euigwae, in which wedding feast dishes for King and prince in Chosun Dynasty were described. The results obtained from the study were as follows, 1. For wedding feast dishes for prince, black lacquered table was used, and for King's wedding feast red lacquered table was used. 2. In wedding ceremony red silk table cloth was used. 3. Tables arranged in wedding ceremony had high legs. 4. Tablewares used in wedding ceremony were footed dishes. 5. Wedding ceremony arrangement was made up of four kinds of main table, a small boiled beef table, a large boiled beef table, four small round tables, a dining table, a candle stick, a incense holder, a vase with vaseholder and a liquor bottle with a holder.

• 한국결정성장학회지
• /
• 제23권4호
• /
• pp.173-179
• /
• 2013

다이아몬드는 원석의 형태가 불규칙하고 견고하더라도 보석으로 쉽게 가공될 수 있으며, 등급 평가에 영향력을 나타내는 테이블, 크라운, 퍼빌리언, 거들면을 정밀하게 측정하였다. Round Brilliant Cut Diamond의 표준 연마에 적합한 규격을 조사하였고, 통계적(95 %) 신뢰 구간으로 표준편차, 평균, 허용 오차를 검토하였다. 측정된 크기, 각도, 깊이, 두께의 변수들이 나타내는 분포에 따라, 커팅 등급의 빈도 분석과 프로포션을 비교하였다. 각 변수간의 상관관계와 프로포션에 나타난 영향력의 근거는 LSM(Least Square Method)을 적용한 회귀 분석으로 결정하였다. 본 논문에서, 다이아몬드의 테이블 크기와 퍼빌리언 깊이 퍼센트가 등급 결정에 많은 영향을 미치고, 특히, 퍼빌리언 깊이는 프로포션과 관련하는 주요 원인으로 광학 현상에도 작용함을 알 수 있었다.

• 정보보호학회논문지
• /
• 제12권2호
• /
• pp.53-64
• /
• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• 정보과학회지
• /
• 제27권2호
• /
• pp.4-14
• /
• 2009

• 기술사
• /
• 제41권6호
• /
• pp.31-37
• /
• 2008

• 한국지반공학회지:지반
• /
• 제28권1호
• /
• pp.8-26
• /
• 2011