• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.112-121
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• 2003

Information Protection and cryptography technology is developed with if but solved problem of real time processing and secret maintain. Therefore this paper is Proposed new PRN-SEED(Pseudo-Random Number-SEED) for the increasing secret rate and processing rate perform performance analysis with existed other cryptography algorithms. Proposed new PRN-SEED crypto-algorithm increase in the processing rate than existed algorithms use bit and byte mixed operation with RNG(Random Number Generator). PRN-SEED that performs simultaneous operations have higher 1.03 in the processing rate and 2 in the cryptosystem performance than existed cryptosystems. Implementation for PRN-SEED use Synopsys Design Analyser Ver. 1999.10, samsung KG75 library and Synopsys VHDL Debegger. As a simulation result, symmetric cryptosystem DES operate 416Mbps at the 40MHz and Rijndael operate 612Mbps at the 50MHz. PRN-SEED cryptosystem have gate counting 10K and operate 430Mbps at the 40MHz and 630Mbps at the 50MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• Journal of Korea Multimedia Society
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• v.5 no.6
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• pp.665-673
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• 2002

In this paper, we introduce cellular automata and propose a new block cipher algorithm based on cellular automata. For the evaluation of performance and security, we compare the results of the proposed algorithm with them of the standard block ciphers such as DES, Rijndael regarding on avalanche effects and processing time, and analyze the differential cryptanalysis for a reduction version of the proposed algorithm. In addition, we perform the statistical tests in FIPS PUB 140-2(Federal Information Processing Standards Publication 140-2) for the output bit sequences of proposed algorithm to guarantee the randomness property.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.771-772
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• 2008

In this paper, we analyze the characterization of Mibench, an embedded system benchmark program, using simplescalar simulator. The experimental results show Mibench generally is formed by lots of integer and memory access instructions. Especially, IPC of rijndael decoding is effected by cache size largely, but IPC of CRC32 is few effected by cache size or branch predicting algorithm.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.285-288
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• 2001

In this paper a design of cryptographic coprocessor which implements AES Rijndael algorithm is described. To achieve average throughput of 1 round per 5 clocks, subround pipelined scheme is applied. To apply the coprocessor to various applications, three key sizes such as 128, 192, 256 bits are supported. The cryptographic coprocessor is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology and consists of about 36, 000 gates. Its peak performance is about 512 Mbps encryption or decryption rate under 200 Mhz clock frequency and 128-bit key ECB mode(AES-128ECB).

• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.624-627
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• 2009

본 논문에서는 차세대 블록 암호 시스템으로 선정되었으며 미연방정부의 표준으로 제정된 RBC(Rijndael Block Cipher) 알고리즘을 하드웨어로 구현하였다. 구현된 블록 암호 시스템은 임베디드 시스템에 적용이 가능하도록 암호화 블록과 복호화 블록을 따로 설계하지 않고 하드웨어를 공유하여 하나의 블록에서 선택에 따라 암호화와 복호화가 모두 이루어질 수 있도록 설계함으로써 하드웨어의 면적을 최소화하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.13-23
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• 2001

This paper implemented into hardware SEED which is the KOREA standard 128-bit block cipher. First, at the respect of hardware implementation, we compared and analyzed SEED with AES finalist algorithms - MARS, RC6, RIJNDAEL, SERPENT, TWOFISH, which are secret key block encryption algorithms. The encryption of SEED is faster than MARS, RC6, TWOFISH, but is as five times slow as RIJNDAEL which is the fastest. We propose a SEED hardware architecture which improves the encryption speed. We divided one round into three parts, J1 function block, J2 function block J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined one round into three parts, J1 function block, J2 function block, J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined it to make it more faster. G-function is implemented more easily by xoring four extended 4 byte SS-boxes. We tested it using ALTERA FPGA with Verilog HDL. If the design is synthesized with 0.5 um Samsung standard cell library, encryption of ECB and decryption of ECB, CBC, CFB, which can be pipelined would take 50 clock cycles to encrypt 384-bit plaintext, and hence we have 745.6 Mbps assuming 97.1 MHz clock frequency. Encryption of CBC, OFB, CFB and decryption of OFB, which cannot be pipelined have 258.9 Mbps under same condition.

• International Journal of Computer Science & Network Security
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• v.22 no.4
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• pp.285-291
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• 2022

With the growing exchange of data between individuals and institutions through various electronic communication, valuable data protection is in high demand to ensure that it is not hacked and that privacy is protected. Many security techniques, such as encryption and steganography, have emerged to prevent security breaches. The purpose of this research is to integrate cryptographic and steganography techniques to secure text message sending. The Rijndael algorithm was used to encrypt the text message, and the Least Significant Bit algorithm was also used to hide the encrypted message in a color image. Experiments on the suggested method have proven that it can improve the security of sent messages due to the human eye's inability to identify the original image from the image after it has been covered, as well as the encryption of the message using a password.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1082-1088
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• 2005

Generating fast round key in AES Rijndael algorithm using three key sizes, such as 128, 192, and 256-bit keys is a critical factor to develop high throughput AES processors. In this paper, we propose on-the-fly round key generator which is applicable to the pipelined and non-pipelined AES processor in which cipher and decipher nodes must be implemented on a chip. The proposed round key generator has modular and area-and-time efficient structure implemented with simple connection of two key expander modules, such as key_exp_m and key_exp_s module. The round key generator for non-pipelined AES processor with support of three key lengths and cipher/decipher modes has about 7.8-ns delay time under 0.25um 2.5V CMOS standard cell library and consists of about 17,700 gates.