• 품질경영학회지
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• 제21권2호
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• pp.35-47
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• 1993

This study was performed to obtain the internal failure cost in the failure and rework using cost table. The manufacturing cost is different according to each production process. Thierefore, it is difficult to calculate of the manufacturing cost. Using the cost table internal failure cost can be calculated easily in each process.

• 대한산업공학회지
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• 제20권1호
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• pp.3-13
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• 1994

The problem of selecting the optimal target values in a canning process is considered for situations where there is a linear shift in the mean of the content of a can which is assumed to be normally distributed with known variance. The target values are initial process mean, length of resetting cycle and controllable upper limit. Profit models are constructed which involve give-away, rework, and resetting costs. Methods of finding the optimal target values are presented and a nemerical example is given.

• 품질경영학회지
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• 제26권3호
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• pp.46-59
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• 1998

The problem of selecting optimal target values for the mean of the quality characteristic of interest for a production process in which an item is sold in one of two market with different profit / cost structures or reworked. Two profit models are constructed which involve four profit / cost components: profit, production, inspection, and rework costs. Assumed that the quality characteristic of interest is normally distributed, methods of finding the most profitable process mean are presented and a numerical example is given.

• 한국경영과학회:학술대회논문집
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• 한국경영과학회 1996년도 추계학술대회발표논문집; 고려대학교, 서울; 26 Oct. 1996
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• pp.166-169
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• 1996

Well-evaluated quality of software can provide business proper decisions, increase productivity, and prevent financial loss or unnecessary burden of rework. Evaluation is important to ensure the chosen software conforming to organizational requirements, customer demands, and product integrity level. In this paper, we present a theoretical model with the structure of evaluation requirements to select the prioritized evaluation target input of software quality. Within limited time and budget, the prioritized target inputs of evaluation can be used to determine the appropriate evaluating step for each different category of requirements.

• 산업경영시스템학회지
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• 제16권28호
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• pp.203-209
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• 1993

In Factory Automation environments such as FMS, the formation of machine-part based on GT should be considered. The purpose of this study is to develop a economic heuristic algorithm which considers various elements such as unit processing time, subcontract cost, and functional operation cost, machine processing capacity etc. When this proposed approach is applied to the real situation expected benefits are as follows: the reduction of production lead time work in process, labor force, tooling, rework and scrap, setup time, order time delivery, and paper work, etc.

• 산업경영시스템학회지
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• 제11권17호
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• pp.81-85
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• 1988

This paper presents a model that considers combinations of rework, repair, replacement and scrapping. Policy-Iteration method of inspection is proposed for a serial manufacturing system whose repair cost, scrap cost and inspection cost. when it fails, can be formulated by Markovian approach. Policy-Iteration stops when new inspection policy is the same as previous inspection policy. A numerial example is presented.

• 품질경영학회지
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• 제26권1호
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• pp.172-191
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• 1998

In this paper, dimension tolerance design for components is studied. Three cost factors are considered: machining cost, rework cost, and loss related to product quality which is affected by the tolerances of components. We propose a procedure to determine the optimal tolerances of components and a, pp.y the procedure to design the tolerances of fine motion stage in semicoduct machine. We compare the proposed procedure with the existing model for determining tolerance economically.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• 한국건축시공학회지
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• 제17권6호
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• pp.535-544
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• 2017

본 논문은 BIM 기반 설계 검토를 통하여 사전에 방지된 설계 오류와 그 영향도를 통계적으로 분석한다. 이를 위하여 한국에서 수행되었던 2개 BIM 프로젝트에서 BIM 기반 설계 검토를 도입함으로써 발견되었던 약 800여건 이상의 설계오류를 설계 오류 발생 원인별(비논리적 오류, 도면 상이, 누락), 발생 공종별(구조, 건축, 설비)로 분류한다. 시공 이전에 발견된 설계 오류로 인하여 발생할 수 있는 재작업과 공사비, 공사기간, 품질에의 영향 여부를 해당 현장의 실무자와의 인터뷰를 통해서 분류하고, 설계 오류와의 확률적 관계를 로지스틱 회귀분석을 이용하여 분석한다. 분석결과, 설계 오류 발생원인이 공사비 증가, 공기 지연, 품질 저하, 재작업을 유발 확률 예측에 통계적으로 가장 유의미한 관계가 있었다. 두 개의 프로젝트에서 수집된 자료만을 활용하여 설계 오류 간의 관계를 분석하였지만 설계 오류의 특성의 관계가 유사하다는 점에서 의미가 있다고 할 수 있다. 향후에는 다수의 프로젝트에서 수집된 자료를 분석하여 이를 검증하고자 한다.