• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.140-140
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• 2010

Non-mass analyzed ion shower doping (ISD) technique with a bucket-type ion source or mass-analyzed ion implantation with a ribbon beam-type has been used for source/drain doping, for LDD (lightly-doped-drain) formation, and for channel doping in fabrication of low-temperature poly-Si thin-film transistors (LTPS-TFT's). We reported an abnormal activation behavior in boron doped poly-Si where reverse annealing, the loss of electrically active boron concentration, was found in the temperature ranges between $400^{\circ}C$ and $650^{\circ}C$ using isochronal furnace annealing. We also reported reverse annealing behavior of sequential lateral solidification (SLS) poly-Si using isothermal rapid thermal annealing (RTA). We report here the importance of implantation conditions on the dopant activation. Through-doping conditions with higher energies and doses were intentionally chosen to understand reverse annealing behavior. We observed that the implantation condition plays a critical role on dopant activation. We found a certain implantation condition with which the sheet resistance is not changed at all upon activation annealing.

• Proceedings of the KSME Conference
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• 2001.06d
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• pp.337-342
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• 2001

A numerical study of three-dimensional fluid flow and heat transfer in the metering section of a single screw extruder has been performed. The mathematical model for the screw channel is simplified by unwound channel and fixing the coordinate system to the screw. The pressure boundary and the prescribed mass flow rate conditions are imposed on the inlet and outlet, respectively. The commercial code STAR-CD based on the finite volume method is used to obtain the results of the present work. The computation of the reverse flow, which cannot be computed by the marching-type 3-D model, is performed in the present study.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.193-196
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• 2002

This paper presents the improvement of the boron penetration and the reverse short channel effect (RSCE) in the 130nm W/WNx/Poly-Si dual gate PMOSFET for a high performance embedded DRAM. In order to suppress the boron penetration, we studied a range in the process heat budget. It has shown that the process heat budget reduction results in suppression of the boron penetration. To suppress the RSCE, we experimented with the halo (large tilt implantation of the same type of impurities as those in the device well) implant condition near the source/drain. It has shown that the low angle of the halo implant results in the suppression of the RSCE. The experiment was supported from two-dimensional(2-D) simulation, TSUPREM4 and MEDICI.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.780-783
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• 1999

This paper gives channel estimation of W-CDMA reverse link using 2-point second-order algorithm over Rayleigh fading channels. The proposed algorithm is compared with the existing interpolation algorithms, i.e., WMSA, linear and second-order Gaussian interpolation, by obtaining HER performance through computer simulations. The BER performance of 2-point second-order interpolation is superior to other algorithms in fading channels. The proposed algorithm also has relatively-simple structure and similar processing delay in comparison to the existing algorithm, Therefore, this algorithm is more suitable for high speed mobile communication environments.

• Water for future
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• v.29 no.2
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• pp.153-165
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• 1996

One-dimensional unsteady flow model including weir flow simulation is studied. Applicabilities of both the single channel model with local treatment of the weir overflow, and the looped-network model are studied using a test problem. It is shown that various type of weir flows including reverse flows are successfully simulated. Flow discontinuity due to the high crest elevation can also be simulated. The reverse free-flowing overflow can be simulated by the single-channel model as well as by the looped-network model.

• Journal of IKEEE
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• v.23 no.3
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• pp.934-940
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• 2019

In this paper, we propose a Reverse Differential Chaos Shift Keying (RE-DCSK) system for low cost, high reliability and high data rate non-coherent chaos communication .In RE-DCSK, reference signals are transmitted in the first slot as in the conventional differential chaos shift modulation scheme (DCSK) and in the second slot a time inversion block strengthens the autocorrelation of the chaos signal and uses the orthogonality of the two signals to obtain the information signal. RE-DCSK enables relatively double the data rate compared to DCSK and also improves the security of communications without any additional cost of system complexity.To prove its effectiveness, we analyze it through Rayleigh fading channel and additional white Gaussian noise (AWGN) channel based on the derived BER expression. The BER performance of the proposed system is improved when compared with the CDSK and DCSK system using AWGN channel.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.5
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• pp.855-867
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• 2022

As the need for a deep learning accelerator increases with the development of IoT equipment, research on the implementation and safety verification of the deep learning accelerator is actively. In this paper, we propose a new side channel analysis methodology for secret information that overcomes the limitations of the previous study in Usenix 2019. We overcome the disadvantage of limiting the range of weights and restoring only a portion of the weights in the previous work, and restore the IEEE754 32bit single-precision with 99% accuracy with a new method using CPA. In addition, it overcomes the limitations of existing studies that can reverse activation functions only for specific inputs. Using deep learning, we reverse activation functions with 99% accuracy without conditions for input values with a new method. This paper not only overcomes the limitations of previous studies, but also proves that the proposed new methodology is effective.

• International Journal of Computer Science & Network Security
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• v.23 no.10
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• pp.1-10
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• 2023

This paper proposes a method to extend Inter-Carrier Interference (ICI) canceling Orthogonal Frequency Division Multiplexing (OFDM) receivers for 5G mobile systems to spatial multiplexing 2×2 MIMO (Multiple Input Multiple Output) systems to support high-speed ground transportation services by linear motor cars traveling at 500 km/h. In Japan, linear-motor high-speed ground transportation service is scheduled to begin in 2027. To expand the coverage area of base stations, 5G mobile systems in high-speed moving trains will have multiple base station antennas transmitting the same downlink (DL) signal, forming an expanded cell size along the train rails. 5G terminals in a fast-moving train can cause the forward and backward antenna signals to be Doppler-shifted in opposite directions, so the receiver in the train may have trouble estimating the exact channel transfer function (CTF) for demodulation. A receiver in such high-speed train sees the transmission channel which is composed of multiple Doppler-shifted propagation paths. Then, a loss of sub-carrier orthogonality due to Doppler-spread channels causes ICI. The ICI Canceller is realized by the following three steps. First, using the Demodulation Reference Symbol (DMRS) pilot signals, it analyzes three parameters such as attenuation, relative delay, and Doppler-shift of each multi-path component. Secondly, based on the sets of three parameters, Channel Transfer Function (CTF) of sender sub-carrier number n to receiver sub-carrier number l is generated. In case of n≠l, the CTF corresponds to ICI factor. Thirdly, since ICI factor is obtained, by applying ICI reverse operation by Multi-Tap Equalizer, ICI canceling can be realized. ICI canceling performance has been simulated assuming severe channel condition such as 500 km/h, 8 path reverse Doppler Shift for QPSK, 16QAM, 64QAM and 256QAM modulations. In particular, 2×2MIMO QPSK and 16QAM modulation schemes, BER (Bit Error Rate) improvement was observed when the number of taps in the multi-tap equalizer was set to 31 or more taps, at a moving speed of 500 km/h and in an 8-pass reverse doppler shift environment.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.22 no.4
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• pp.217-239
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• 2018

This paper examined the MHD and thermal behavior of unsteady mixed convection flow of a rotating fluid in a porous parallel plate channel in the presence of Hall current and heat source. The exact solutions of the concentration, energy and momentum equations are obtained. The influence of each governing parameter on non dimensional velocity, temperature, concentration, skin friction coefficient, rate of heat transfer and rate of mass transfer at the porous parallel plate channel surfaces is discussed. During the course of numerical computation, it is observed that as Hall current parameter and Soret number at the porous channel surfaces increases, the primary and secondary velocity profiles are increases while the primary and secondary skin friction coefficients are increases at the cold wall and decreases at the heated wall. In particular, it is noticed that a reverse trend in case of heat source parameter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1289-1295
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• 2007

In this paper, we implemented high-performance concurrent control system which manages whole RF systems with digital type and communicates with remote station on both wire and wireless networking. It consists of FPGA (Field Programmable Gate Array) part which controls forward/reverse LPA (Linear Power Amplifier), forward/reverse LNA (Low Noise Amplifier), channel cut wire/wireless TCP/IP, etc, master microprocessor (AVR), which manages the whole control system, Slave microprocessor which communicates SA (Spectrum Analyzer) and observes frequency spectrum of each channel with the resolution of 5KHz, 10 channel card microprocessor which independently observes each channel card and sets frequency synthesizer in channel cut and other peripherals and logics. The whole system is divided to two parts of H/W (hardware) and S/W (software) considering operational efficiency and concurrency, and implementation and cost. H/W consists of FPGA and microprocessor. We expected the optimized operation through H/W and SW co-design and hybrid H/W architecture.