• 한국진공학회지
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• 제5권4호
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• pp.333-340
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• 1996

Cu 확산방지막으로서의 Tin의 특성을 면저항 특정, X선 회절 분석, SEM, AES, capacitance-voltage(C-V) 측정에 의하여 평가하고, Cu의 확산을 민감하게 알아내는 정도를 특성 평가 방법간에 비교하였다. 여러 가지 증착방법에 의하여 Cu/TiN/Ti/SiO2/Si 구조의 다층 박막시편을 제작하였으며, 이 시편을 10% H2/90% Ar분위기, 열처리 온도 500~$800{\circ}C$ 범위에서 2시간 동안 열처리하였다. TiN의 Cu 확산방지 효과가 소멸된 경우 Cu 박막 표면에서 불규칙한 모양의 spot을 관찰할 수 있었으며 outdiffusion된 Si를 검출할 수 있었다. MOS capacitor의 C-V 특성은 열처리 온도에 따라 급격하게 변화하였다. C-V 측정에서 inversion capacitance는 열처리 온도 500~$700^{\circ}C$범위에서 열처리 온도가 높아질수록 감소하다가 $800^{\circ}C$에서 크게 증가하였으며, 이러한 특성의 변화는 TiN을 통해서 $SiO_2$와 Si내로 확산된 Cu에 의하여 발생되는 것으로 생각된다.

• 전자공학회논문지
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• 제52권4호
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• pp.88-95
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• 2015

본 논문에서는 부성저항을 생성하는 회로로 알려진 RFNR 회로에 대한 새로운 분석을 소개한다. 새로운 분석에서는 RFNR 회로에 대한 수식분석의 정확성을 높이기 위해 트랜지스터의 게이트 저항과 소스 커패시턴스에 의한 영향을 고려하였다. 기존의 분석에서는 트랜지스터의 소스를 통하여 수식을 분석하였지만 제안된 수식에서는 회로의 공진부인 트랜지스터의 게이트를 통하여 회로를 분석했다. 그 결과, 제안하는 분석은 고주파수에서 기존의 분석보다 정확도를 향상시킬 수 있었다. 본 논문에서는 시뮬레이션을 통해 고주파수에서 분석의 정확도를 검증하였다.

• 한국의류학회지
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• 제45권1호
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• pp.168-179
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• 2021

This study presents and develops a textile type touch sensor structural design that is easy to implement. First, the design of the touch sensor circuit finds the size of the switch with the easiest finger contact and selects a structure with a long circuit with the lowest resistance value. An experiment is performed on a change in an electrostatic capacitance value that accompanies the distance on the electrode and the magnitude of the electrode area of the structure; however, the structure having the distance on the electrode and the large electrode area shows the best resistance change. The laundry assessment was conducted three times at a time and ten times at a time with an average standard deviation less than one ohm, with little change in resistance. Consequently, there were no problems with durability and performance for laundry. Finally, in the bending evaluation, the difference in resistance can be seen between 1-2 ohms and was developed as a smart wearable in the future; in addition, there was no problem as a difference in resistance can be seen between 1 and 2 ohms.

• 한국세라믹학회지
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• 제31권8호
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• pp.869-873
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• 1994

Electrical properties of each interfacial layers on semiconducting ceramics have been analized and evaluated by complex impedance resonance method as functions of ambient temperatures and applied voltages. From the analytical results, it can be observed that the interfacial layers in a semiconducting ceramics vary individually with the ambient temperature and then this influence the total properties. Also, it has been confirmed that the applied voltage on semiconducting ceramics affect mainly the electrode interface, and thus the resistance and capacitance decrease due to the variation of potential barrier layers.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1293-1296
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• 2008

As Flat Panel Display become large in format, the data and gate lines turn into longer, parasitic capacitance and resistance increase, and the display signal is delayed. Three dimensional architecture of multiplexing data registration integrated circuit method is used that divides the data line into several blocks and provides the advantages of high accuracy, rapid selection, and reasonable switching speed.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1564-1567
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• 2008

We demonstrate here a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100 - 400 nm. A perfected down-scaled polymer transistors (L= 200 nm) showing high transition frequency over 1.5 Mhz were realized with thin polymer dielectrics, controlling contact resistance, and minimizing overlap capacitance via self-aligned gate configuration.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.763-766
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• 2003

A direct parameter extraction method using several two-port parameter equations derived in cutoff and active bias modes has been studied to obtain an accurate Gummel-Poon BJT model. First, dc model parameters were extracted from slopes and y-axis intercepts of I-V curve and Gummel plot. The pad capacitances and junction capacitance parameters were determined by using measured S-parameter sets in the cutoff bias. The resistance and transit time parameters were extracted by using measured S-parameter sets in the active bias.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2002년도 학술대회지
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• pp.713-716
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• 2002

Aging effect on the cardiovascular circulation is simulated by lumped parameter model. Aging phenomena can be hemodynamically explained as (1) the increase of flow resistance induced by remodeling of artery vessels and increased viscosity of blood and (2) the reduction of the vessel capacitance caused by arteriosclerosis. Appropriate physiological parameters are evaluated from the clinical data of adults and old men. Simulation results well explain the hypertension with aging of cardiovascular system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.181-184
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• 1999

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.13-14
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• 2000

21.6" a-Si:H TFT array for direct conversion X-ray detector with 2480 by 3072 pixel is successfully developed. To obtain good X-ray image quality, novel structure, storage on BCB structure, is proposed. The structure reduces the parasitic capacitance of data line, one of the main sources of signal noise. Also, the structure shows higher failure resistance against defects than that of the old design.