• Journal of the Korean Vacuum Society
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• v.5 no.4
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• pp.333-340
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• 1996

The properties of TiN as a barrier against Cu diffusion ere studied by sheet resistance measurement, X-ray diffraction, scanning electron microscopy, Auger electron spectroscopy, and capacitance-voltage(C-V) measurement. The sensitivities of the various methods were compared. Specimens with Cu/TiN/Ti/SiO2/Si structure were prepared by various deposition techniques and annealed at various temperatures ranging from $500^{\circ}C$ to $800^{\circ}C$ in 10%H2/90%Ar ambient for hours. As the effectiveness of the barrier property of TiN against Cu diffusion was vanished, the irregular-shaped sports were observed and outdiffused Si were detected on the surface of the Cu thin film. The C-V characteristics of the MOS capacitors varied drastically with annealing temperatures. In C-V measurement, the inversion capacitance decreased at annealing temperature range from $500^{\circ}C$ to $700^{\circ}C$ and increased remarkably at $800^{\circ}C$. These variations may be due to the Cu diffusion through TiN into $SiO_2$ and Si.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.88-95
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• 2015

This paper presents a new analysis of RF negative resistance (RFNR) circuits, known as a negative resistance generator. For accurate equation analysis of RFNR, this study examined the effects of the gate resistance and the source parasitic capacitance of the transistor. In addition, the input admittance of the conventional equation was calculated by looking into the source-terminal of the transistor, whereas that of the proposed equation was calculated by examining the gate-terminal of the transistor. The proposed equation analysis is more accurate than that of the conventional analysis, especially for higher frequency range. This paper verify the accuracy of the proposed analysis at high frequency range using the simulation.

• Journal of the Korean Society of Clothing and Textiles
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• v.45 no.1
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• pp.168-179
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• 2021

This study presents and develops a textile type touch sensor structural design that is easy to implement. First, the design of the touch sensor circuit finds the size of the switch with the easiest finger contact and selects a structure with a long circuit with the lowest resistance value. An experiment is performed on a change in an electrostatic capacitance value that accompanies the distance on the electrode and the magnitude of the electrode area of the structure; however, the structure having the distance on the electrode and the large electrode area shows the best resistance change. The laundry assessment was conducted three times at a time and ten times at a time with an average standard deviation less than one ohm, with little change in resistance. Consequently, there were no problems with durability and performance for laundry. Finally, in the bending evaluation, the difference in resistance can be seen between 1-2 ohms and was developed as a smart wearable in the future; in addition, there was no problem as a difference in resistance can be seen between 1 and 2 ohms.

• Journal of the Korean Ceramic Society
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• v.31 no.8
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• pp.869-873
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• 1994

Electrical properties of each interfacial layers on semiconducting ceramics have been analized and evaluated by complex impedance resonance method as functions of ambient temperatures and applied voltages. From the analytical results, it can be observed that the interfacial layers in a semiconducting ceramics vary individually with the ambient temperature and then this influence the total properties. Also, it has been confirmed that the applied voltage on semiconducting ceramics affect mainly the electrode interface, and thus the resistance and capacitance decrease due to the variation of potential barrier layers.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1293-1296
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• 2008

As Flat Panel Display become large in format, the data and gate lines turn into longer, parasitic capacitance and resistance increase, and the display signal is delayed. Three dimensional architecture of multiplexing data registration integrated circuit method is used that divides the data line into several blocks and provides the advantages of high accuracy, rapid selection, and reasonable switching speed.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1564-1567
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• 2008

We demonstrate here a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100 - 400 nm. A perfected down-scaled polymer transistors (L= 200 nm) showing high transition frequency over 1.5 Mhz were realized with thin polymer dielectrics, controlling contact resistance, and minimizing overlap capacitance via self-aligned gate configuration.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.763-766
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• 2003

A direct parameter extraction method using several two-port parameter equations derived in cutoff and active bias modes has been studied to obtain an accurate Gummel-Poon BJT model. First, dc model parameters were extracted from slopes and y-axis intercepts of I-V curve and Gummel plot. The pad capacitances and junction capacitance parameters were determined by using measured S-parameter sets in the cutoff bias. The resistance and transit time parameters were extracted by using measured S-parameter sets in the active bias.

• Proceedings of the KSME Conference
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• 2002.08a
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• pp.713-716
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• 2002

Aging effect on the cardiovascular circulation is simulated by lumped parameter model. Aging phenomena can be hemodynamically explained as (1) the increase of flow resistance induced by remodeling of artery vessels and increased viscosity of blood and (2) the reduction of the vessel capacitance caused by arteriosclerosis. Appropriate physiological parameters are evaluated from the clinical data of adults and old men. Simulation results well explain the hypertension with aging of cardiovascular system.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.181-184
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• 1999

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.13-14
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• 2000

21.6" a-Si:H TFT array for direct conversion X-ray detector with 2480 by 3072 pixel is successfully developed. To obtain good X-ray image quality, novel structure, storage on BCB structure, is proposed. The structure reduces the parasitic capacitance of data line, one of the main sources of signal noise. Also, the structure shows higher failure resistance against defects than that of the old design.