• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.1
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• pp.33-38
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• 2021

Using facing target magnetron sputtering (FTMS) with a graphite target source, carbon nitride thin films were deposited on silicon and glass substrates at different substrate temperatures to confirm the tribological, electrical, and structural properties of thin films. The substrate temperatures were room temperature, 150℃, and 300℃. The tribology and electrical properties of the carbon nitride thin films were measured as the substrate temperature increased, and a study on the relation between these results and structural properties was conducted. The results show that the increase in the substrate temperature during the fabrication of the carbon nitride thin films increased the hardness and elastic modulus values, the critical load value was increased, and the residual stress value was reduced. Moreover, the increase in the substrate temperature during thin-film deposition was attributed to the improvement in the electrical properties of carbon nitride thin film.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.322-329
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• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2004.05a
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• pp.337-341
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• 2004

Engineering ceramics have superior heat resistance, corrosion resistance, and wear resistance. Consequently, these art significant candidates for hot-section structural components of heat engine and the inner containment of nuclear fusion reactor. Besides, some of them have the ability to heal cracks and great benefit can be anticipated with great benefit the structural engineering field. Especially, law fracture toughness of ceramics supplement with self-healing ability. In the present study, we have been noticed some practically important points for the healing behavior of silicon nitride, alumina, mullite with SiC particle and whisker. The presence of silicon carbide (SiC) in ceramic compound is very important for crack-healing behavior. However, self-healing of SiC has not been investigated well in detail yet. In this study, commercial SiC was selected as sample, which can be anticipated in the excellent crack healing ability. The specimens were produced three-point bending specimen with a critical semi-circular crack of which size that is about $50-700{\mu}m$. Three-point bending test and static fatigue test were performed cracked and healed SiC specimens. A monotonic bending load was applied to cracked specimens by three-point loading at different temperature. The purpose of this paper is to report Strength Properties and Elastic Waves Characteristics of Silicon Carbide with Crack Healing Ability.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.313-313
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• 2013

For high-performance TFT (Thin film transistor), poly-crystalline semiconductor thin film with low resistivity and high hall carrier mobility is necessary. But, conventional SPC (Solid phase crystallization) process has disadvantages in fabrication such as long annealing time in high temperature or using very expensive Excimer laser. On the contrary, MIC (Metal-induced crystallization) process enables semiconductor thin film crystallization at lower temperature in short annealing time. But, it has been known that the poly-crystalline semiconductor thin film fabricated by MIC methods, has low hall mobility due to the residual metals after crystallization process. In this study, Ni metal was shallow implanted using PIII&D (Plasma Immersion Ion Implantation & Deposition) technique instead of depositing Ni layer to reduce the Ni contamination after annealing. In addition, the effect of external magnetic field during annealing was studied to enhance the amorphous silicon thin film crystallization process. Various thin film analytical techniques such as XRD (X-Ray Diffraction), Raman spectroscopy, and XPS (X-ray Photoelectron Spectroscopy), Hall mobility measurement system were used to investigate the structure and composition of silicon thin film samples.

• Journal of Sensor Science and Technology
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• v.7 no.1
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• pp.73-82
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• 1998

In silicon surface micro-machining, the newly developed GPE(gas-phase etching) process was verified as a very effective method for the release of highly compliant micro-structures. The developed GPE system with anhydrous HF gas and $CH_{3}OH$ vapor was characterized and the selective etching properties of sacrificial layers to release silicon micro-structures were discussed. P-doped polysilicon and SOI(silicon on insulator) substrate were used as a structural layer and TEOS(tetraethyorthdsilicate) oxide, thermal oxide and LTO(low temperature oxide) as a sacrificial layer. Compared with conventional wet-release, we successfully fabricated micro-structures with virtually no process-induced striction and residual product.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.499-499
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• 2011

Silicon nanowires (Si NWs) have been extensively studied for nanoelectronics owing to their unique optical and electrical properties different from those of bulk silicon. For the development of Si NW devices, better understanding of oxidation behavior in Si NWs would be an important issue. For example, it is widely known that atomic scale roughness at the dielectric (SiOx)/channel (Si) interface can significantly affect the device performance in the nano-scale devices. However, the oxidation process at the atomic-scale is still unknown because of its complexity. In the present work, we investigated the oxidation behavior of Si NW in atomic scale by simulating the dry oxidation process using a reactive molecular dynamics simulation technique. We focused on the residual stress evolution during oxidation to understand the stress effect on oxidation behavior of Si NWs having two different diameters, 5 nm and 10 nm. We calculated the charge distribution according to the oxidation time for 5 and 10 nm Si NWs. Judging from this data, it was observed that the surface oxide layer started to form before it is fully oxidized, i.e., the active diffusion of oxygen in the surface oxide layer. However, it is well-known that the oxide layer formation on the Si NWs results in a compressive stress on the surface which may retard the oxygen diffusion. We focused on the stress evolution of Si NWs during the oxidation process. Since the surface oxidation results in the volume expansion of the outer shell, it shows a compressive stress along the oxide layer. Interestingly, the stress for the 10 nm Si NW exhibits larger compressive stress than that of 5 nm Si NW. The difference of stress level between 5 an 10 anm Si NWs is approximately 1 or 2 GPa. Consequently, the diameter of Si NWs could be a significant factor to determine the self-limiting oxidation behavior of Si NWs when the diameter was very small.

• Clean Technology
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• v.18 no.1
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• pp.43-50
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• 2012

Cleaning procedure of solar silicon wafer, following ingot sawing process in solar cell production is studied. Types of solar silicon wafer can be divided into monocrystalline or multicrystalline, and slurry sawn wafer or diamond sawn wafer according to the ingot growing methods and the sawing methods, respectively. Wafer surface and contaminants can vary with these methods. The characterisitics of contaminants and wafer surface are investigated for each cleaning substrate, and appropriate cleaning agents are developed. Physical properties and cleaning ability of the cleaning agents are evaluated in order to verify the application in the industry. The wafers cleaned with the cleaning agents do not show any residual contaminants when analyzed by XPS and regular patterns are formed after texturization. Furthermore, the cleaning agents are applied in the production industry, which shows superior cleaning results compared to the existing cleaning agents.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1158-1161
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• 2004

This paper presents structural characteristics of station class lightning arresters and electrical characteristics of manufactured ZnO varistor blocks which are usable in those arresters. Three types of station class lightning arresters were investigated and those are a ceramic arrester, a FRP tube type polymer arrester, and a FRP rod type polymer arrester. Each arrester has merits and demerits with structural characteristics. In general, polymer arresters were made of silicon rubber for housing materials, FRP tube or rod for mechanical strength, ZnO blocks for electrical characteristics, and metal parts for electrical contact and the silicon rubber, the housing materials, was directly injected to the arrester module which was assembly composed of electrodes, ZnO blocks and FRP tube or rod, and to prevent the nonlinear electric fields distribution on upper parts of arresters, the grade ring was adopted to the upper electrodes. The reference voltage, nonlinear coefficient, residual voltage, and voltage ratio of manufactured ZnO varistors are 4.90kV, 50, 9.54kV, 1.94, respectively. Compared to designed electrical characteristics, the reference voltage was low for 600v and the voltage ratio was slightly high. However, the characteristics of discharge withstand was so excellent that the mechanical destruction does not occur at the impulse current of $8/20{\mu}s$ 10kA for 100 times.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.3
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• pp.273-277
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• 2005

We prepared $0.25\~l.5um$ poly silicon gate array test group with $SiO_2$ spacers in order to employ NiCo composite salicide process from 15nm Ni/15nm Co/poly structure. We investigate the residual metal shape evolution by varying the rapid thermal silicide anneal temperature from $700^{\circ}C\;to\;1100^{\circ}C$. We observed the residual metals agglomerated into maze type and line type on $SiO_2$ field and silicide gate, respectively as temperature increased. We propose that lower silicide temperature would be favorable in newly proposed NiCo salicide in order to lessen the agglomeration causing the leakage and scum formation.

• Journal of the Korean Ceramic Society
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• v.52 no.6
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• pp.410-416
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• 2015

Recently, a new $Y_2O_3$ coating deposited using the EB-PVD method has been developed for erosion resistant applications in fluorocarbon plasma environments. In this study, surface crack formation in the $Y_2O_3$ coating has been analyzed in terms of residual stress and elastic modulus. The coating, deposited on silicon substrate at temperatures higher than $600^{\circ}C$, showed itself to be sound, without surface cracks. When the residual stress of the coating was measured using the Stoney formula, it was found to be considerably lower than the value calculated using the elastic modulus and thermal expansion coefficient of bulk $Y_2O_3$. In addition, amorphous $SiO_2$ and crystalline $Al_2O_3$ coatings were similarly prepared and their residual stresses were compared to the calculated values. From nano-indentation measurement, the elastic modulus of the $Y_2O_3$ coating in the direction parallel to the coating surface was found to be lower than that in the normal direction. The lower modulus in the parallel direction was confirmed independently using the load-deflection curves of a micro-cantilever made of $Y_2O_3$ coating and from the average residual stress-temperature curve of the coated sample. The elastic modulus in these experiments was around 33 ~ 35 GPa, which is much lower than that of a sintered bulk sample. Thus, this low elastic modulus, which may come from the columnar feather-like structure of the coating, contributed to decreasing the average residual tensile stress. Finally, in terms of toughness and thermal cycling stability, the implications of the lowered elastic modulus are discussed.