• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.53-59
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• 1994

A new fully differential sample-and-hold circuit which can effectively compensate the offset voltage of an operational amplifier and the charge injection of a MOS switch is presented. The proposed circuit shows a true sample-and-hold function without a reset period or an input-track period. The prototype fabricated using a 1.2$\mu$m double-polysilicon CMOS process occupies an area of 550$\mu$m$\times$288$\mu$m and the error of the sampled ouput is 0.056% on average for 3V input at DC.

• Progress in Superconductivity
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• v.5 no.1
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.439-446
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• 2004

This paper describes high speed and low power design techniques for an 8-bit 500MSamples/s CMOS 2-step ADC. Instead of the conventional closed-loop architecture, the newly proposed ADC adopts open-loop architecture and uses a reset-switch to reduce loading time in an environment of big parasitic-capacitances of mux-array. An analog-latch is also used to reduce power consumption. Simulation result shows that the ADC has the SNDR of 46.91㏈ with a input frequency of 103MHz at 500Msample/s and consumes 203㎽ with a 1.8V single power supply. The chip is designed with a 0.18mm 1-poly 6-metal CMOS technology and occupies active area of 760${\mu}{\textrm}{m}$*800${\mu}{\textrm}{m}$.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.1
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• pp.54-60
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• 2011

The flight control law designed for prototype aircraft often leads to degraded stability and performance, although developed control law verify by non-real time simulation and pilot based evaluations. Therefore, the proper evaluation methods should be applied such that flight control law designed can be verified in real flight environment. The one proposed in this paper is IFS (In-Flight Simulator). Currently, this system has been implemented into the F-18 HARV (High Angle of Attack Research Vehicle), SU-27 and F-16 VISTA (Variable stability In flight Simulation Test Aircraft) programs. The IFS necessary switching control law such as fader logic and integrator stand-by mode to reduce abrupt transient and minimize the integrator effect for each flight control laws switching. This paper addresses the concept of switching mechanism with fader logic of "TFS (Transient Free Switch)" and stand-by mode of "feedback type" based on SSWM (Software Switching Mechanism). And the result of real-time pilot evaluation reveals that the aircraft is stable for inter-conversion of flight control laws and transient response is minimized.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.7
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• pp.694-702
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• 2007

The SSWM(Software Switching Mechanism) of I-processor concept using non-real time in-house software simulation program is an effective method in order to develop the flight control law in desktop or HQS environment. And, this system has some advantages compare to HSWM(Hardware Switching Mechanism) such as remove the time delay effectiveness and reduce the costs of development. But, if this system loading to the OFP(Operational Flight Program), the OFP guarantee the enough throughput in order to calculate the two control law at once. Therefore, the HSWM(Hardware Switching Mechanism) of 2-processor concept is necessary. This paper addresses the concept of HSWM of the HQS-PC interface using TCP/IP(Transmission Control Protocol/Internet Protocol) communication based on flight control law of advanced supersonic trainer. And, the fader logic of TFS(Transient Free Switch) and stand-by mode of reset '0' type are designed in order to reduce the abrupt transient response and minimize the integrator effect in pitch axis. The result of the analysis based on HQS pilot simulation using HSWM reveals that the flight control systems are switching between two computers without any problem.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.6
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• pp.89-98
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• 2010

Isolated boost converter is desirable in the dc/dc converter applications where isolation is required and extremely high step up is needed. Transformer used to step up low input voltage into high output voltage must satisfy the volt-sec balance condition. Conventional isolated boost converter is controlled with conducting intervals overlapping. In this case, there is a problem that control circuit is complicated. In this paper, it is proposed and analyzed the isolated boost converter which set up a reset winding for the volt-sec balance of transformer and can construct the control circuit simple by using a self-driven switch. Finally, the validity of the theoretical analyses for the proposed converter is verified by both simulations and experiments on the 10[W] class isolated boost converter.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.7
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• pp.711-719
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• 2008

Although non-real time simulation and pilot based evaluations are available for the development of flight control computer prior to real flight tests, there are still many risky factors. The control law designed for prototype aircraft often leads to degraded performance from the initial design objectives, therefore, the proper evaluation methods should be applied such that flight control law designed can be verified in real flight environment. The one proposed in this paper is IFS(In-Flight Simulator). Currently, this system has been implemented into the F-18 HARV(High Angle of Attack Research Vehicle), SU-27 and F-16 VISTA(Variable stability. In flight Simulation Test Aircraft) programs. This paper addresses the concept of switching mechanism for FLCC(Flight Control Computer)-SWMC(Switching Mechanism Computer) using 1553B communication based on flight control law of advanced supersonic trainer. And, the fader logic of TFS(Transient Free Switch) and stand-by mode of reset '0' type are designed to reduce abrupt transient and minimize the integrator effect in pitch axis control law. It hans been turned out from the pilot evaluation in real time that the aircraft is controllable during the inter-conversion process through the flight control computer, and level 1 handling qualities are guaranteed. In addition, flight safety is maintained with an acceptable transient response during aggressive maneuver performed in severe flight conditions.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.951-954
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• 2003

본 논문에서는 고속. 저전력에 적합한 개방 구조를 갖는 8-비트 500Msmaples/s 2-Step ADC 를 제안하였다. 500Msmaples/s 의 고속 동작을 위해서 기존의 M-DAC을 이용한 폐쇄 구조 대신 개방형 구조를 사용하였다. 이와 더불어 저전력을 구현하기 위해서 analog-latch 를 제안하여 동적 동작을 수행시킴으로써 전력 소모를 줄였으며 , mux 의 구현 시 reset switch를 이용하여 로딩 시간을 개선함으로써 high-speed 에 적합하도록 설계하였다. 제안된 ADC 는 1-poly 6-metal 0.18um CMOS 공정을 이용하였으며 1.8V 전원 전압을 이용하여 250mW 의 전력을 소모하며 500M 샘플링 주파수에서 120MHz 신호 입력 시 7.6 비트의 ENOB를 얻을 수 있었다.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.376-377
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• 2010

In this paper, novel unidirectional auxiliary resonant commutated pole is proposed to improve the performance of zero-voltage soft-switching inverter. The proposed circuit keeps the advantages of the original soft-switching inverter, while providing more effective resetting capability in magnetizing current. Based on the advanced reset mechanism, auxiliary switches operate under a complete zero-current condition. The operating principle and steady-state analysis are presented theoretically, according to its operating modes. Accordingly, it proves the fact that the proposed unidirectional auxiliary resonant commutated pole breaks an unwanted magnetizing current loop effectively. The performance of the proposed circuit is verified by several simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6B
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• pp.423-432
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• 2012

We design a control circuit that can switch input power between a rechargeable battery and a sensor communication device (mote) depending on the operating state of a solar cell as well as the active and sleep mode of a sensor MAC protocol. A mote that simply combines a solarcell and a rechargeable battery may die if there is not sunlight long. A battery is recharged if sunlight is sufficient and a device is in a sleep mode, and it supplies power if sunlight is low and the mote is in an active mode. A mote can switch its input power between solar cell and battery depending on the output level of a solar cell. During this switching, a mote may lose its state information due to the reset of a microprocessor by the transient power-off. A capacitor is used to cope with this phenomenon and also supplies power to a mote during a sleep mode. Experimental results show that the solar cell based mote operates in a very stable manner against the lack of sunlight long.