• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2014년도 하계학술대회
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• pp.157-159
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• 2014

In this paper, we introduce SlimSRP, an ultra-low-power digital signal processor (DSP) solution for mobile audio and voice applications. So far, application processors (APs) have taken charge of all the tasks in mobile devices. However, they have suffered from short battery life problems to deal with complex usage scenarios, such as always-on voice trigger with continuous audio playback. From extensive analysis of audio and voice application characteristics, SlimSRP is designed to relive the performance and power burden of APs. It employs three-issue VLIW architecture, and the major low-power and high-performance techniques include: (1) an optimized register-file architecture friendly for constants generation, (2) a powerful instruction set to reduce the number of register file accesses and (3) a unique instruction compression scheme that contributes to saved memory size and reduced cache miss. An implementation of SlimSRP runs at up to 200MHz and the logic occupies 95K NAND2 gates in Samsung 28LPP process. The experimental results demonstrate that a MP3 decoder application with a 128kbps 44.1kHz input can run at 5.1MHz and the logic consumes only 22uW/MHz.

• 한국정보통신학회논문지
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• 제26권10호
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• pp.1537-1544
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• 2022

application specific integrated circuit (ASIC) 및 system on chip (SoC) 설계 시 디지털 회로는 클럭에 동기화되어 작동한다. 칩 설계 시, place & route (P&R)에서 설계 조건과 타이밍 조건, 클럭의 동기화 여부 등을 고려한다. P&R에서 클럭 경로에 대한 delay를 줄이기 위해, clock tree synthesis (CTS) 기법을 이용한다. 본 논문에서는 사전 클럭트리 합성 가능 여부 판단을 위한 shallow-CTS 알고리즘을 소개한다. 오픈 소스 Parser-Verilog를 사용하여 register transfer level (RTL) 합성가능한 Verilog를 파싱하여, Pre-CTS와 Post-CTS 단계를 진행하고, 가장 긴 clock path와 버퍼 삽입 전후의 표준편차를 비교하여 CTS의 정확도에 대해 분석한다. 본 논문에서 시간 투입이 많이 되는 licensed EDA tool을 사용하여 CTS 결과를 확인하지 않고, RTL 수준에서 사전 클럭 트리 합성 검증 방법을 제공하여 비용 및 시간문제를 감소할 수 있을 것으로 기대된다.

• 한국CDE학회논문집
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• 제19권1호
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• pp.41-49
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• 2014

For the reuse of the existing 3D block model of a ship, we analyze the hull modeling process using AVEVA Marine which is a representative CAD (Computer-Aided Design) system for the shipbuilding. In the AVEVA Marine environment where the design engineer makes 3D model on the 2D view that is so-called 2.5D, it cannot be possible to copy to reuse the block model just simply copying the 3D feature model itself like in the general mechanical CAD system or Smart Marine 3D which are on the basis of the 3D model representation. In this paper, we analyze the scheme file where the 3D model is defined in AVEVA Marine so that we develop the program for the block copy and the translation using this scheme file. It is significant that this program can be immediately available as a real-world application on the AVEVA Marine environment.

• ETRI Journal
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• 제26권6호
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• 한국멀티미디어학회논문지
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• 제9권12호
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• pp.1681-1688
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• 2006

GIS systems have gradually been utilized in life information as well as special businesses such as traffic, sight-seeing, tracking, and disaster services. Most GIS services focus on showing stored information on maps, not providing a service to register and modify their preferred information. In this paper, we present a new method which reduces DXF map data into Simple Geographic Information File format using format conversion algorithms. We also present the prototype implementation of a GIS search system based on ontologies to support associated information. Our contribution is to propose a new digital map format to provide a fast map loading service and individual customized information on the map service.

• 대한전자공학회논문지
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• 제27권8호
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• pp.1201-1210
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• 1990

This paper proposes on-chip instruction and data cache memories on RISC reduced instruction set computer) architecture which supports fast instruction fetch and data read/write, and enables RISC processor under research to obtain high performance. In the execution of HLL(high level language) programs, heavily used local scalar variables are stored in large register file, but arrays, structures, and global scalar variables are difficult for compiler to allocate registers. These problems can be solved by on-chip Instruction/Data cache. And each cycle of instruction fetch, pad delay causes the lowering of the processors's performance. Cache memories are designed in CMOS technology and SRAM(static-RAM), that saves layout area and power dissipation, is used for instruction and data storage. To speed up and support RISC processor's piplined architecture efficiently, hardwired logic technology is used overall circuits i cache blocks. The schematic capture and timing simulation of proposed cache memorises are performed on Apollo DN4000 workstation using Mentor Graphics CAD tools.

• 전자공학회논문지B
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• 제28B권7호
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• pp.508-519
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• 1991

A new heuristic two-dimensional symbolic layout compaction approach is developed. After conventional one-dimensional compaction steps, all the components on the critical paths that define the height or width of the given layout are found and rearranged to reduce layout size. During this process, constraints in both x and y directions are considered and pitch-matching of ports for hierarchical compaction can be achieved to reduce the amount of the design data. This approach generated the smallest area for several examples we have tried when compared with other published results. The expected run time can be bouned by OT$_1$, where T$_1$ is the run time of a typical one-dimensional compactor.

• 전자공학회논문지C
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• 제35C권2호
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• pp.1-9
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• 1998

To achieve high performance in VLIW processors, they must exploit the parallelism on application programs. Data dependency makes it difficult to find the instruction-level parallelism. Among the three kinds of data dependency, true dependency causes RAW(Read After Wirte) hazards that occur most frequently in VILW processors. Forwarding is a widely used technique to reduce the performance degradation caused by RAW hazards. However, forwarding requires too much area of the chip when it is applied to VLIW processors. In this paper, static forwarding is proposed to reduce the hardware cost of forwarding circuits. It needs an extended compiler to detect RAW hazards and control the proposed forwarding scheme via instruction. And it uses the modified register file to shrink the area of forwarding path. VLIW Processor Model is also designed to verify static forwarding. This paper describes the operation of static forwarding and the comparison with the conventional forwarding.

• 전자공학회논문지A
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• 제31A권10호
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• pp.141-151
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• 1994

this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

• 전자공학회논문지A
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• 제33A권5호
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• pp.172-179
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• 1996

In the paper, QCELP (qualcomm code excited linear predictive), CDMA (code division multiple access)'s vocoder algorithm, was analyzed. And then, a ptich parameter seaarch architecture for 16-bit programmable DSP(digital signal processor) for QCELP was designed. Because we speed up the parameter search through high speed DSP using two MACs, we can satisfy speech codec specifiction for the digital celluar. Also, we implemented in FIFO(first-in first-out) memory using register file to increase the access time of data. This DSP was designed using COMPASS, ASIC design tool, by top-down design methodology. Therefore, it is possible to cope with rapid change at mobile communication market.