효율적인 그래프를 이용한 이차원 레이아웃 컴팩숀 알고리듬

Design of a Register File and its Peripheral Circuit for RISC

A new heuristic two-dimensional symbolic layout compaction approach is developed. After conventional one-dimensional compaction steps, all the components on the critical paths that define the height or width of the given layout are found and rearranged to reduce layout size. During this process, constraints in both x and y directions are considered and pitch-matching of ports for hierarchical compaction can be achieved to reduce the amount of the design data. This approach generated the smallest area for several examples we have tried when compared with other published results. The expected run time can be bouned by OT$_1$, where T$_1$ is the run time of a typical one-dimensional compactor.