• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.953-956
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• 2000

Application specific DSPs often employ irregular datapath structures with distributed registers. In the scheduling phase of retargetable compilation, resolution of register usage conflicts comes to be a new constraint for such datapaths. This paper presents a method of register constraint analysis which attempts to minimize the number of the spill codes required for resolving the register usage conflicts. It searches for a set of ordering restrictions among operations which sequentialize the lifetimes of the values residing in the same register as much as possible and thus minimize the number of the register conflict. Experimental results show that a combination of the proposed register constraint, analysis and list-based scheduling reduces the number of the register spills into 25%.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1211-1220
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• 1990

This paper describes and implements a design method of register allocation as a required module of RISC compiler systems. It compiles a C program to a machine-independent intermediate language, translates each variable into symbolic register. After local allocation process for the symbolic registers, global register allocation is executed by applying the graph coloring algorithm. This register allocation phase is designed for a system with the large register file like RISC machines.

• Journal of Korean Library and Information Science Society
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• v.20
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• pp.241-284
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• 1993

Through the restoration, we can find that the register of houses, inhabitants and their ancestry, which is in the Sunsung Kim family registers, was fundamentally the census register of Kim Roe including more ancestry transformed into the lists of house, inhabitants and their ancestry of Kim Roe, Kim Bang-Seek, Kim Sung-Sae and Kim Hee-Bo. And we can find also the original forms were considerably damaged. That is, in the course of transformation, considerable parts of the contents of ancestry were not needed, so they were removed, the recordings of brotherandsisters, sons and their servants were also removed. By comparing of the restored census register of Kim Roe and the Sunsung Kim family registers, we can know the fact that when they published the family registers, the contents of the founder to the ninth descendants were totally depended on the census register of Kim Roe. The Census Register of King Taejo of Choson Dynasty(National Treasure No. 131) which has been recorded almost same periods as the census register of Kim Roe was remained as an original state. Therefore, it was greatly helpful for restoring the census register of Kim Roe. There were few materials which we can know the way of ordinary life in Koryo period. But through the census register of Kim Roe and the census Register of King Taejo of Choson Dynasty, we have a glimpse of their life history. Nevertheless we can find some demerits in the census register of Kim Roe as followers : First, it is not an original but a transformed one, while the Census Register of King Taejo of Choson Dynasty is first materials. Second, it was recorded the only one family. Finally, it was omitted the parts of his brotherandsisters, children and servants who lived with their master. According to these demerits its worth of materials for history will be descended more or less. Therefore, when we use this material, we should treat it more considerably.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.81-88
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• 2007

In on-line transaction, the transparency is the key factor for the taxation and customer's rights. Using the cash register concept of the off-line transaction, we studied on-line transaction register model for the e-commerce transparency. Although on-line transaction register may be used under the related e-commerce laws, in this paper, we only considered the mechanism of the register. The register issues the digital receipt, and then the receipt can be verified the validation by the models developed in this paper.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.121-130
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• 2011

Recent research indicates that transient errors will increasingly become a critical concern in microprocessor design. As embedded processors are widely used in reliability-critical or noisy environments, it is necessary to develop cost-effective fault-tolerant techniques to protect processors against transient errors. The register file is one of the critical components that can significantly affect microprocessor system reliability, since registers are typically accessed very frequently, and transient errors in registers can be easily propagated to functional units or the memory system, leading to silent data error (SDC) or system crash. This paper focuses on investigating the impact of register file soft errors on system reliability and developing cost-effective techniques to improve the register file immunity to soft errors. This paper proposes the register vulnerability factor (RVF) concept to characterize the probability that register transient errors can escape the register file and thus potentially affect system reliability. We propose an approach to compute the RVF based on register access patterns. In this paper, we also propose two compiler-directed techniques and a hybrid approach to improve register file reliability cost-effectively by lowering the RVF value. Our experiments indicate that on average, RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly, without sacrificing the register value integrity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.763-773
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• 2003

In this paper, we present a register renaming method for conditional execution out-of-order instruction issue microprocessors. Register renaming method reduces false data dependencies (write after read(WAR) and write after write(WAW)). To implement a conditional execution out-of-order instruction issue microprocessor using register renaming, we use a register file which includes both in-order state physical registers and look-ahead state physical registers to share all logical registers. And we design an in-order state indicator, a renaming state indicator, a physical register assigning indicator, a condition prediction buffer and a reorder buffer. As we utilize the above hardwares, we can do register renaming and trace the in-order state. In this paper, we present an improved register renaming method using smaller hardware resources than conventional register renaming method. And this method eliminates an associative lookup and provides a short recovery time.

• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.494-496
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• 2013

In this paper, we introduce a technique for delayed deallocation of temporary register allocation. We achieve faster binary translation that is used in the context of register allocation. By delaying deallocation of the temporary register containing the value, it is preserved until the next instruction fetched. If subsequent instruction does not require the value again, binary translator deallocate and release the temporary register at the first stage of the next instruction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.85-94
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• 2004

In this paper, a register allocation techlique that translates memory accesses to register accesses Is presented to enhance embedded software performance. In the proposed method, a source code is profiled to generate a memory trace. From the profiling results, target functions with high dynamic call counts are selected, and the proposed register allocation technique is applied only to the target functions to save the compilation time. The memory trace of the target functions is searched for the memory accesses that result in cycle count reduction when replaced by register accesses, and they are translated to register accesses by modifying the intermediate code and allocating Promotion registers. The experiments where the performance is measured in terms of the cycle count on MediaBench and DSPstone benchmark programs show that the proposed method increases the performance by 14% and 18% on the average for ARM and MCORE, respectively.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.51-54
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• 2000

In this paper, an compiler system is ported and modified for register allocation experiments. This compiler system will enable various global register allocation. Lcc is introduced and Chaitin's graph coloring algorithm is executed with cmcc on DEC ALPHA 255/300. Several functions of SPEC921NT is used as inputs of the compiler system.