• 대한기계학회논문집A
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• 제25권12호
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• pp.2009-2018
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• 2001

This paper presents a region offsetting algorithm for tool-path generation. The proposed region offsetting algorithm is developed by expanding the 'PWID offset algorithm [Choi and Park, 1999]'designed to offset a simple polygon. The PWID offset algorithm has three important steps; 1) remove 'local invalid ranges'by invoking a PWID test, 2) construct a raw offset owe and 3) remove 'global invalid ranges'by finding self-intersections of the raw offset cure. To develop a region offsetting algorithm, we modified the PWID offset algorithm by expanding the concept of the 'global invalid range'in the third step. The time complexity of the proposed algorithm is approximately Ο(n), where n is the number of points, and it is free of numerical errors for practical purposes. The proposed algorithm has been implemented and tested with various real regions obtained by intersecting a sculptured surface with a plane.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.26-29
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• 1999

The I-V characteristics of the n-channel offset gated poly-Si TETs have been systematically investigated in order to analyse the effects of offset region. The on currents are reduced due to the series resistance by the offset length and there is no kink phenomenon in offset devices. The off currents of the offset gated TFTs are remarkably reduced to 10$^{-12}$ A independent of gate and drain voltage because the electric field is weakened by the increase of the depletion region width near the drain region. It is shown that the offset regions behave as a series resistance and reduce lateral and vertical electric field.

• 전자공학회논문지A
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• 제33A권7호
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• pp.127-133
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• 1996

In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photoresist reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate form both sides of the main gate. The poly-Si channel layer below the offset oxide is protected form the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of oru new device is the offset region due to the offset oxide. our experimental reuslts show that the offset region, due to the photoresist reflow process, has been sucessfully obtained in order to fabricate the offset gated poly-Si TFTs. The maximum ON/OFF ratio occurs at the L$_{off}$ of 1.1${\mu}$m and exceeds 1X10$^{6}$.

• 태양에너지
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• 제8권2호
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• pp.57-65
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• 1988

The coefficients of convective heat transfer were investigated when air is jetted to surface of the heated side-wall. The temperature on the side-wall was measured when the offsets changed from 1.5 to 10.5 as 7 steps at the state of fixed Reynolds numbers that were 35000, 29000 and 23000. The experimental results are as follows: 1. The mean Nusselt number is very high on the surface of reattached flow region. 2. The offset and the recirculation flow region decreased, while the mean Nusselt number increased between the outlet of nozzle and the region of reattachment flow. 3. The local Nusselt number is not concerned with Reynolds number on the recirculation flow and on the reattached flow region when the offset decrease. But the Nusselt number increased only when Reynolds numbers on the wall jet flow region increased. 4. The mean and the maximum Nusselt number decreases linearly, and in particular its values rapidly decrease in accordance with changing of the offset from 1.5 to 3 in inverse proportion.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.141-144
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• 1998

The electrical characteristics of poly-Si TFT's with offset structure by negative bias stress are systematically investigated as a function of offset length. The changes of electrical characteristics, V$\_$th/, off-current, on/off ratio, in the offset structured poly-Si TFT's are smaller than that of the conventional structured poly-Si TFT's under the stress condition (V$\_$ds/=20V, V$\_$gs/=-20V). It is found that the hot carrier effect by negative bias stress is suppressed by the offset structured poly-Si TFT's because the local electric field near the drain region is decreased by offset region.

• 한국전기전자재료학회논문지
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• 제13권2호
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• pp.101-105
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• 2000

The effects of electrical on n-channel offset gated poly-Si TFT's have been investigated. It is observed that the electrical field near the drain region in offset devices is smaller than that of conventional device by simulation results. The variation rate of threshold voltage and subthreshold slope decrease with increasing the offset length because of lowering the electric field near the drain region. The offset gated poly-Si TFT's have been probed effective in reducing the degradation rate of device performance under electrical stressing.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.457-460
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• 1999

The effects of electrical positive stress on n-channel LDD and offset structured poly-Si TFT\`s have been systematically investigated in order to analyze the transfer curve\`s shift mechanism. It has been found that the LDD and offset regions behave as a series resistance that reduce the electric field near drain. Hot carrier effects are reduced because of these results. After electrical stress transfer curve’s shift and variation of the off-current are dependent upon the offset length rather than offset region’s doping concentration. Variation of the subthreshold slope is dependent upon offset region’s doping concentration as well as offset length.

• Journal of Electrical Engineering and Technology
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• 제10권1호
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• pp.138-145
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• 2015

In this paper, a novel static overmodulation scheme (OVM) for space-vector PWM (SVPWM) is proposed. The proposed static OVM scheme uses the concept of adding offset voltages in linear region as well as overmodulation region to fully utilize DC-link voltage. By employing zero sequence voltage injection, the proposed scheme reduces procedures for achieving SVPWM such as complicated gating time calculation. In addition, this paper proposes a stepwise discontinuous angle movement in high modulation region in order to reduce Total Harmonic Distortion (THD). The validity of the proposed scheme is verified through theoretical analysis and experimental results.

• 천문학회보
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• 제37권1호
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• pp.33.2-33.2
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• 2012

Low-ionization nuclear emission-line region (LINER) galaxies constitute a major fraction of low-luminosity AGN population in the local Universe. In contrast to Seyfert galaxies, it is theoretically expected that LINERs would not have an outflow due to their low Eddington ratio. Using Keck/LRIS spectroscopy on a nearby LINER galaxy SDSS J091628.05+420818.7, we find a significant radial velocity offset for [OIII]${\lambda}$5007 emission line as - 50 km $s^{-1}$ blueshifted compared to systemic velocity of the galaxy, while other emission lines exhibit no or little offset. The observed [OIII] velocity offset possibly indicates an outflow of gas in the LINER galaxy, and it is probable that we only detected the [OIII] velocity offset because [OIII] ionization region is closer to the accretion disk, hence, more affected by an outflow. We further investigate the [OIII] velocity offset of -4000 SDSS AGN-host galaxies to compare the strength of AGN outflow. We find that a number of both LINER and Seyfert galaxies show [OIII] velocity offset, but the fraction of LINER galaxies with velocity offset is smaller than that of Seyfert galaxies. The preliminary results imply the presence of gas outflow in LINER galaxies, although outflow strength is probably weaker compared to Seyfert galaxies.