• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.76-76
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• 2009

눈부신 전자산업의 발달로 대부분의 전자제품이 다기능/경박단소화 되고 있어, 고밀도 실장 기술인 양면 표면실장과 고집적 패키징 기술인 패키지 적층 공정의 적용이 점차 확대되고 있다. 따라서 양면 표면실장 및 패키지 적층 공정에 사용되는 저온 접합용 무연 솔더 즉, $183^{\circ}C$(Sn-37Pb 공정 솔더 융점) 이하의 융점을 가지는 저온 무연 솔더에 대한 관심이 높아지고 있다. 한편, 미세피치 적용 분야에 있어 ACF/P를 이용한 COG 접속 분야 외에도 최근 저온 접합용 무연 솔더를 이용한 접속 분야가 각광을 받고 있다. 따라서, 접속피치 미세화에 대응하기 위해 스크린 인쇄성을 향상시킬 수 있는 저온 무연 솔더 paste 제조 및 공정 기술의 개발이 필요한 실정이다. 현재 대표적인 저온 무연 솔더 조성은 Sn-Bi계($138^{\circ}C$ 융점)와 Sn-In계($120^{\circ}C$ 융점)이다. 하지만, 이들 조성의 신뢰성 등에 있어 개선의 여지가 있으므로 이를 해결하기 위한 무연솔더 조성의 개발이 필요하다. 이와 같은 관점에서, 본 연구는 $137^{\circ}C$의 융점을 갖는 Sn-57.6Ag-0.4Ag 저온 무연 솔더 paste를 $217^{\circ}C$의 융점을 갖는 Sn-3.0Ag-0.5Cu 솔더 paste와 비교하여 인쇄성, reflow 특성, void inspection, 미세조직 관찰 및 underfill 적용 등의 실험을 실시하였다.

• Transactions of the Korean Society of Automotive Engineers
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• v.21 no.1
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• pp.145-153
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• 2013

In this study, shear punch-creep (SP-Creep) at Sn-4Ag/Cu pad the joint was tested by using environment-friendly Pb-free solder alloy Sn-4Ag of electronic components. Pb eutectic alloy (Sn-37Pb) joints limited to environmental issues with reflow time (10sec, 30sec, 100sec, 300sec) according to two types of solder alloy joints are compared and evaluated by creep strain rate, rupture time and IMC (Intermetallic Compound) behavior. As the results, reflow time increases with increasing thickness of IMC can be seen at overall 100sec later in case of two solder joints on the IMC thickness of Sn-4Ag solder joints thicker than Sn-37Pb solder joints. In addition, when considering creep evaluation factors, lead-free solder alloy Sn-4Ag has excellent creep resistance more than Pb eutectic alloy. For this reason, the two solder joints, such as in the IMC (Cu6Sn5) was formed. However, the creep resistance of Sn-4Ag solder joints was largely increased in the precipitation strengthening effect of dispersed Ag3Sn with interface more than Sn-37Pb solder joints.

• Clean Technology
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• v.11 no.4
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• pp.205-211
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• 2005

There have been many technologies and materials proposed for realizing microlens array, and plastic injection is recognized as the most promising one because of several merits such as optical properties, impact resistance, formability, lightening and environmental adaptability. Since PR reflow for injection template fabrication enables the lens shape control easier, and the sample technology more effective for mass production, it lowers the cost, enhances integration, and reduces process steps, which leads to be environmentally benign. However injection of polymers may face the difficulty of formability depending on their properties. In order to overcome the difficulty, fast heating/cooling technology was introduced in this study, and microlenses were fabricated and evaluated. template obtained by PR reflow method was heated and cooled fast during injection to fabricate microlens array. PC and PMMA polymer materials were compared, and it was realized that PMMA showed much better formability due to its lower melting temperature. Injection parameters of pressures and velocities were driven out for injection optimization.

• Korean Journal of Optics and Photonics
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• v.16 no.4
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• pp.340-344
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• 2005

Microlens cells of Ge-doped BPSG (Boro-Phospho-Silicate Glass) are fabricated by dicing the film produced by FHD (Flame Hydrolysis Deposition). Microlens arrays of $53.4{\mu}m$ square unit are produced by the thermal reflow of the diced unit cells at $1200^{\circ}C$. The gap between the microlenses was about $70{\mu}m,$ and the thickness of the produced lens was about $28.4{\mu}m$. We analyzed the reflowed shape of the microlens cell by an image-process technique, and the focal length was about $62.2{\mu}m$. This method of fabricating a microlens is simple and inexpensive compared to the conventional method using the photolithographic process. Also, the control of the radius of curvature of the microlens is easier and a more precise microlens way of various types can be fabricated using this method.

• Korean Journal of Metals and Materials
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• v.48 no.11
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• pp.1041-1046
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• 2010

The reactions between a Sn-3.0Ag-0.5Cu solder alloy and electroless Ni/electroless Pd/immersion Au (ENEPIG) surface finishes with various Pd layer thicknesses (0, 0.05, 0.1, 0.2, $0.4{\mu}m$) were examined for the effect of the Pd layer on the massive spalling of the $(Cu,Ni)_6Sn_5$ layer during reflow at $235^{\circ}C$. The thin layer deposition of an electroless Pd (EP) between the electroless Ni ($7{\mu}m$) and immersion Au ($0.06{\mu}m$) plating on the Cu substrate significantly retarded the massive spalling of the $(Cu,Ni)_6Sn_5$ layer during reflow. Its retarding effect increased with an increasing EP layer thickness. When the EP layer was thin (${\leq}0.1{\mu}m$), the retardation of the massive spalling was attributed to a reduced growth rate of the $(Cu,Ni)_6Sn_5$ layer and thus to a lowered consumption rate of Cu in the bulk solder during reflow. However, when the EP layer was thick (${\geq}0.2{\mu}m$), the initially dissolved Pd atoms in the molten solder resettled as $(Pd,Ni)Sn_4$ precipitates near the solder/$(Cu,Ni)_6Sn_5$ interface with an increasing reflow time. Since the Pd resettlement requires a continuous Ni supply across the $(Cu,Ni)_6Sn_5$ layer from the Ni(P) substrate, it suppressed the formation of $(Ni,Cu)_3Sn_4$ at the $(Cu,Ni)_6Sn_5/Ni(P)$ interface and retarded the massive spalling of the $(Cu,Ni)_6Sn_5$ layer.

• Transactions of Materials Processing
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• v.17 no.5
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• pp.322-327
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• 2008

LGP is a key component of LCD back light unit because it determines brightness and sharpness of the display image. Usually, it has optical patterns fabricated on the bottom surface. These optical patterns convert point or line sources placed in the side of LGP to plane source at the top surface by changing the propagating direction of the incident light. In the present paper the LiGA-reflow method was applied to fabricate the LGP mold. Furthermore, the optical simulation considering the replication ratio of pattern height was applied to the pattern design. The optical simulation through systematic correction scheme was adopted to find the optimum distribution of pattern density. Finally, the stamper fabricated by this method was installed in the mold and LGP was produced by injection molding. As a result of luminance measurement for the final product, the average luminance and luminance uniformity was measured 3,180 nit and 84%, respectively. Consequently, the mold fabrication method using the LiGA-reflow and optical simulation(CAE) can save the expense and time compared with the existing fabrication methods(laser ablation and chemical etching).

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.351-357
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• 2005

Comparison of shear strength and shear energy of the 48Sn-52In solder bumps reflowed on Cu UBM were made with variations of reflow temperature from $150^{\circ}C$ to $250^{\circ}C$ and reflow time from 1 min to 20 min to establish an evaluation method for the mechanical reliability of solder bumps. Compared to the shear strength, the shear energy of the Sn-52In solder bumps was much more consistent with the solder reaction behavior and the fracture mode at the Sn-52In/Cu interface, indicating that the bump shear energy can be used as an effective tool to evaluate the mechanical integrity of solder/UBM interface.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1582-1584
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• 1996

The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.

• Journal of Welding and Joining
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• v.19 no.3
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• pp.305-310
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• 2001

UBM-coated Si-wafer was fluxlessly soldered with glass substrate in $N_2$ atmosphere using plasma cleaning method. The bulk Sn-37wt.%Pb solder was rolled to the sheet of $100\mu\textrm{m}$ thickness in order to bond a solder disk by fluxless 1st reflow process. The oxide layer on the solder surface was analysed by AES(Auger Electron Spectroscopy). Through rolling, the oxide layer on the solder surface became thin, and it was possible to bond a solder disk on the Si-wafer with fluxless process in $N_2$ gas. The Si-wafer with a solder disk was plasma-cleaned in order to remove oxide layer formed during 1st reflow and soldered to glass by 2nd reflow process without flux in $N_2$ atmosphere. The thickness of oxide layer decreased with increasing plasma power and cleaning time. The optimum plasma cleaning condition for soldering was 500W 12min. The joint was sound and the thicknesses of intermetallic compounds were less than $1\mu\textrm{m}$.