• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.226-228
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• 2006

This paper presents a comparative study of single-phase PLL algorithms using virtual 2-phase strategy. Simulation and experimental results, including operation of the PLL structures introduced in reference papers, are presented to allow a performance comparison of the PLL algorithms.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.2
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• pp.107-113
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• 1987

A complete design of a new digital control circuit for a three-phase controlled rectifier is presented. The circuit consists of a gating signal generating ROM, down counter and adder. Proposed scheme is simple and quite adequate to the microprocessor-based digitally controlled systems. The basic principle and operation characteristics of the circuit are described and experimental-results show good dynamic performance. Synchronization problem with noisy reference is also discussed. The basic phylosophy developed can be extended to the other phase control system, e.g., cycloconverters, ac voltoge controllers, etc.

• Journal of electromagnetic engineering and science
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• v.3 no.1
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• pp.62-66
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• 2003

Novel coupled line phase shifters and its equivalent phase delay line for compact broadband phased array antennas are proposed. These phase control circuits are designed to be less complex, small size and to use a less number of active devices. The phase shifter is able to control a 120$^{\circ}$ phase shift continuously, and the phase delay line for a reference phase has a fixed 60$^{\circ}$ shifted phase. Both have the low phase error of less than $\pm$3.5$^{\circ}$ and the low gain variations of less than 1 ㏈ within the 300 MHz bandwidth. These proposed circuits are adequate to form the efficient beam-forming networks with compactness, broadband, less complexity, and low cost.

• Journal of Electrical Engineering and Technology
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• v.8 no.4
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• pp.729-736
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• 2013

Power grids are large complicated networks in use around. An absolute phase value for a particular unknown-phase line at a local site should be identified for the operation and management of a 3-phase distribution network. The phase shift for a specific point in the line, as compared with a phase reference point at a substation, must be within a range of ${\pm}60^{\circ}$ for correct identification. However, the phase shift at a particular point can fluctuate depending on the line constants, transformer wiring method, line length, and line amperage, etc. Conducted in this study is a theoretical formulation for the determination of phase at a specific point in the line, Simulink modeling, and analysis for a distribution network. In particular, through evaluating the effects of unbalanced current loads, the limitations of the present phase identification methods are described.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.37-43
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• 2001

In this paper, we propose a new optical security technique using two phase masks based on interferometer. A binary random phase image is used as a reference image and the encrypted image is generated according to the phase difference between the reference image and the original image. If there is no phase difference of a same pixel position in two phase masks, interference intensity of the pixel has minimum value and if phase difference of a same pixel position in two phase masks is $\pi$, its interference intensity has maximum value. We can decrypt the original image by putting two phase masks on each of the two optical paths of the Mach-Zehnder interferometer. Computer simulation and the optical experiments show a good performance of the proposed optical security system.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.5
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• pp.508-517
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• 2005

This paper describes a high performance voltage controller for 3-phase 4-wire UPS (Uninterruptible Power Supply) system, and proposes a new scheme of synchronous reference frame controller in order to compensate for the voltage distortions due to unbalanced and nonlinear loads. Proposed scheme can eliminate the negative sequence voltage component due to unbalanced loads and also reduce the harmonic voltage component due to non-linear loads, even when the bandwidth of voltage control loop is a very low. In order to compensate for the effects of unbalanced loads, the synchronous reference frame controller with the positive and negative sequence computation block is proposed, and the synchronous frame controller with a bandpass filter is proposed to compensate for the selected harmonic frequency of output voltage. The effectiveness of the proposed scheme has been investigated and verified through computer simulations and experiments by a 30kVA UPS.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.233-236
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• 2005

Phase noise in a phase-locked-loop (PLL) is unwanted and unavoidable. It is a main concern in oscillation system especially PLL. The phase noise is derived in term of power spectrum density by using a reliable phase noise model. There are four noise sources being considered in this paper, which are generated by reference oscillator, voltage controlled oscillator, filter, and main divider. The major concern for this paper is the noise from the filter. Two types of second order low pass filter are used in the PLL system. Applying the mathematical phase noise model, the output noises are compared. The total noise from the passive filter is lower than the active filter at the offset frequency range between 1 Hz to 33 kHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1272-1280
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• 2008

In this paper, we have proposed a phase noise model of fast frequency hopping synthesizer with DDS Driven PLL architecture. To accurately model the phase noise contribution of noise sources in frequency hopping synthesizer, they were investigated using model of digital divider for PLL, DAC for DDS and Leeson's model for reference oscillator and VCO. Especially it was proposed that the noise component of low pass filter was considered together with the phase noise of VCO. Under assuming linear operation of a phase locked loop, the phase noise transfer functions from noise sources to the output of synthesizer was analyzed by superposition theory. The proposed phase noise prediction model was evaluated and its results were compared with measured data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.540-549
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• 2017

A phase frequency detector(PFD) composed of logic circuits is widely used in a phase locked loop(PLL) due to the easy implementation for integrated circuits. A frequency locked loop(FLL) removes the reference oscillator in the PLL, and the resonator serves as a reference oscillator. A frequency detector(FD) is indispensable for the FLL configuration, and a FD, which is usually composed of a mixer is used to build an FLL. In this paper, instead of FD using mixer, a FD is constructed by using 1.175 GHz resonator composed of microstrip and PFD taking the versatility of PFD into consideration. Using the designed FD, FLL oscillating at a frequency of 1.175 GHz is composed. As a result of comparison with the FLL composed of FD using mixer, it was confirmed that the proposed FLL has better phase noise performance than FLL using mixer FD with FLL bandwidth.

• PNF and Movement
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• v.19 no.2
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• pp.195-203
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• 2021

Purpose: Neurodynamic tests are used to examine neural tissue in patients with neuro-musculoskeletal disorders, although this has not yet been established in the intensity of nerve tension application. This study aimed to investigate the acute effects of neural stretching intensity on nerve excitability using the latency and amplitude of nerve conduction velocity test (NCV) analysis. Methods: Thirty young, healthy male and female subjects (mean age = 21.30 years) voluntarily participated in this study. Nerve excitability was assessed using the median sensory NCV test. The latency and amplitude of the NCV test were measured under four different conditions: reference phase (supra-maximal stimulus, without neural stretching), baseline phase (2/3 of the supra-maximal stimulus, without neural stretching), weak stretch phase (2/3 of the supra-maximal stimulus, with weak neural stretching), and strong stretch phase (2/3 of the supra-maximal stimulus, with strong neural stretching). Results: The NCV latency was significantly delayed after one minute of neural stretching at the baseline, weak phase, and strong phase in comparison with the reference phase. The NCV latency was significantly delayed by increasing the strength of neural stretching. Furthermore, the NCV amplitude was significantly increased at the weak and strong phases, which were under neural stretching, in comparison with the baseline phase. The NCV amplitude was significantly increased by increasing the strength of the neural stretching. Conclusion: Transient neural stretching as a neurodynamic test can increase the sensitivity of the nerve without negatively affecting the nervous system. However, based on the results of this study, strong neural stretching in the neurodynamic test may delay the transmission of nerve impulses and hypersensitivity.