• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.150-156
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• 2001

This paper proposed a speed estimator using MRAC(Model Reference Adaptive Control) for sensorless vector control. It is robust for parameter variation or disturbance and the estimated speed is used as feedback in a vector control system. Experiment is presented to confirm the theoretical analysis.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.3
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• pp.126-131
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• 2002

This paper is proposed to position and speed control of interior permanent magnet synchronous motor(IPMSM) drive without mechanical sensor. The rotor position, which is an essential component of any vector control schemes, is calculated through the instantaneous stator flux position and an estimated flux value of rotating reference frame. A closed-loop state observer is implemented to compute the speed feedback signal. The validity of the proposed sensorless scheme is confirmed by simulation and its dynamic performance is examined in detail.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.8
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• pp.602-605
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• 2004

A novel motion vector re-estimation technique for transcoding into lower spatial resolution is proposed. This technique is based on the fact that the block matching error is proportional to the complexity of the reference block with Taylor series expansion. It is shown that the motion vectors re-estimated by the proposed method are closer to optimal ones and offer better quality than those of previous techniques.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.79-87
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• 2008

This paper proposes the design and implementation of a direct torque controlled induction motor drive system. The method is based on control of decoupling between amplitude and angle of reference stator flux for determining reference stator voltage vector in generating PWM output voltage for induction motors. The objective is to reduce electromagnetic torque ripple and stator flux droop which result in a decrease in current distortion in steady state condition. In addition, the proposed technique provides simplicity of a control system. The direct torque control is based on the relationship between instantaneous slip angular frequency and rotor angular frequency in adjustment of the reference stator flux angle. The amplitude of the reference stator flux is always kept constant at rated value. Experimental results are illustrated in this paper confirming the capability of the proposed system in regards to such issues as torque and stator flux response, stator phase current distortion both in dynamic and steady state with load variation, and low speed operation.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.55-63
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• 1997

The purpose of this paper is to realize robust vector control of an induction motor without speed sensor. In order to do it, the speed of an induction motor is estimated using model reference adaptive system(MRAS) and two rotor flux observers which have robustness to the parameter variation are employed as the reference model and the adjustable model in MRAS speed estimator. The MRAS-based overall control scheme has been implemented on 2.2kW induction motor control system and it is verified that the proposed speed sensorless control scheme is more stable and robust than the conventional schemes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.100-103
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• 2008

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.108-111
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• 2008

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder engine for real time Full HD video compression. Since there are 384 data coefficients which are sum of 376 AC coefficient and 8 DC coefficient per one macroblock, 384 coefficient have to be processed per one macroblock in worst case for real time processing. We propose an novel architecture which includes parallel architecture and pipeline processing, and reduction "0" in AC/DC coefficient table. To verify the proposed architecture, we develop the reference C for CAVLC and verified the designed circuit with the test vector from reference C code.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.112-115
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• 2008

In this paper, we propose H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18um process including SRAM memory.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.237-240
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• 2005

This paper propose an novel CAVLC architcture for H.264 and designed the CAVLC module which can be used in AMBA based design. This designed module can be operated in 420 cycle for one-macroblock and support both long-start code method using Annex B.1 and RTP. To verify the CAVLC architecture, we developed the reference C from JM8.5 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 54MHz clock system, and has 14096 gate counts using Hynix 0.35 um TLM process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2647-2654
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• 2009

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800K gate counts using Charterd 0.18 um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.