• Journal of Electrical Engineering and Technology
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• v.7 no.1
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• pp.1-8
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• 2012

The current paper presents a novel control strategy of a three-phase, four-wire Unified Power Quality (UPQC) to improve power quality. The UPQC is realized by the integration of series and shunt active power filters (APF) sharing a common dc bus capacitor. The realization of shunt APF is carried out using a three-phase, four-leg Voltage Source Inverter (VSI), and the series APF is realized using a three-phase, three-leg VSI. To extract the fundamental source voltages as reference signals for series APF, a zero-crossing detector and sample-and-hold circuits are used. For the control of shunt APF, a simple scheme based on the real component of fundamental load current (I $Cos{\Phi}$) with reduced numbers of current sensors is applied. The performance of the applied control algorithm is evaluated in terms of power-factor correction, source neutral current mitigation, load balancing, and mitigation of voltage and current harmonics in a three-phase, four-wire distribution system for different combinations of linear and non-linear loads. The reference signals and sensed signals are used in a hysteresis controller to generate switching signals for shunt and series APFs. In this proposed UPQC control scheme, the current/voltage control is applied to the fundamental supply currents/voltages instead of fast-changing APF currents/voltages, thus reducing the computational delay and the required sensors. MATLAB/Simulink-based simulations that support the functionality of the UPQC are obtained.

• Journal of Power Electronics
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• v.16 no.1
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• pp.297-309
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• 2016

Grid-connected inverters (GCIs) with an LCL output filter have the ability of attenuating high-frequency (HF) switching ripples. However, by using only grid-current control, the system is prone to resonances if it is not properly damped, and the current distortion is amplified significantly under highly distorted grid conditions. This paper proposes a synchronous reference frame equivalent proportional-integral (SRF-EPI) controller in the αβ stationary frame using the parallel virtual resistance-based active damping (PVR-AD) strategy for grid-interfaced distributed generation (DG) systems to suppress LCL resonance. Although both a proportional-resonant (PR) controller in the αβ stationary frame and a PI controller in the dq synchronous frame achieve zero steady-state error, the amplitude- and phase-frequency characteristics differ greatly from each other except for the reference tracking at the fundamental frequency. Therefore, an accurate SRF-EPI controller in the αβ stationary frame is established to achieve precise tracking accuracy. Moreover, the robustness, the harmonic rejection capability, and the influence of the control delay are investigated by the Nyquist stability criterion when the PVR-based AD method is adopted. Furthermore, grid voltage feed-forward and multiple PR controllers are integrated into the current loop to mitigate the current distortion introduced by the grid background distortion. In addition, the parameters design guidelines are presented to show the effectiveness of the proposed strategy. Finally, simulation and experimental results are provided to validate the feasibility of the proposed control approach.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.25-35
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• 1998

The control system architecture in switching systems have undergone numerous changes to provide various call processing capability needed in telecommunication services. During call processing in a distributed switching control environment, the delay effect due to communication among main processors or peripheral controllers is one of the limiting factors which affect the system performance. In this paper, we propose a performance model for an IPC(Inter Processor Communication) interface hardware block which is required on the ATM cell-based message processing in a distributed ATM exchange system, and analyze the primary causes which affect the processor performance through the simulation. Consequently, It can be shown that the local CPU of the several components(resources) related to the IPC scheme is a bottleneck factor in achieving the maximum system performance from the simulation results, such as the utilization of each processing component according to the change of the input message rate, and the queue length and processing delay according to input message rate. And we also give some useful results such as the maximum message processing capacity according to the change of the performance of local CPU, and the local CPU maximum throughput according to the change of average message length, which is applicable as a reference data for the improvement or expansion of the ATM control system.

• Food Science of Animal Resources
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• v.32 no.5
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• pp.571-577
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• 2012

This study was carried out to develop an analytical method for the determination of vitamin D in infant formula. Vitamin D was determined by column-switching high-performance liquid chromatography (HPLC) equipped with a reversed phase column and UV detector after saponification and extraction of the formula with an organic solvent. A preseparation column ($C_8$), focusing column ($C_{18}$), analytical column ($C_{18}$) and UV-Vis detector (254 nm) were used. The limits of detection (LOD) and the limits of quantification (LOQ) for vitamin D were estimated to be $1.51{\mu}g/kg$ and $4.95{\mu}g/kg$, respectively. The linearity, recovery, precision and accuracy of the analytical method for vitamin D were evaluated through the application of a SRM (Standard Reference Material) 1846 (National Institute of Standard & Technology, USA). The linearity of this method was calculated with a value of the coefficient of determination ($r^2$) ${\geq}0.9999$. The recovery of vitamin D was $85.20{\pm}3.00%$. The intra-assay precision for vitamin D was between $1.68{\pm}0.03%$ and $5.75{\pm}0.33%$, and the inter-assay precision for vitamin D ranged from $1.73{\pm}0.03%$ to $2.96{\pm}0.09%$. The intra-assay accuracy for vitamin D was between $100.03{\pm}2.77%$ and $102.01{\pm}0.59%$, and the inter-assay accuracy for vitamin D ranged from $99.00{\pm}1.53%$ to $102.01{\pm}3.04%$. The proposed method is optimal for the separation and quantification of vitamin D from infant formula.

• Journal of the Korean Applied Science and Technology
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• v.34 no.4
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• pp.717-726
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• 2017

The current allowable cross-contamination level of fatty acid methyl esters (FAME) in aviation turbine fuel (AVTUR) is 50 mg/kg, due to that the presence of FAME in AVTUR can significantly impact the fuel supply system and jet engine. It has been difficult to analyze the level of FAME in AVTUR, since it is consisted of a lot of hydrocarbons. In this study, thus, a new method using multi-dimensional GC-MS (MDGC-MS) was proposed in order to determine the FAME level in AVTUR effectively. Applying to MDGC-MS with Deans switching system enabled us to detect and quantify the FAME with low carbon numbers such as those derived from coconut oil and palm kernel oil. The matrix effect of MDGC-MS method, which could shift the FAME peaks to slightly longer retention times, was reduced by 20 times compared with that of 1-dimensional GC-MS reference method. This developed method could be suitable for qualitative and quantitative analyses to determine the contamination level of trace FAME in AVTUR.

• Journal of Power Electronics
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• v.12 no.1
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• pp.58-66
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• 2012

SRMs(Switched Reluctance Motors) are much interested in high speed applications due to the mechanical robustness, simple structure and high efficiency. In spite of many advantages of SRMs, a higher torque ripple discourages the adoption of SRMs in a high speed application. This paper presents a simple negative torque of tail current compensation scheme using a modified TSF(Torque Sharing Function) for the high speed SRMs. Because of the short commutation in the high speed region, the negative torque from the tail current makes the high torque ripple. In order to reduce and compensate the negative torque from tail current, the proposed control scheme produces an additional compensating torque with a reference torque in the active phase winding. And the compensating value is dependent on the tail current of the inactive phase winding. Furthermore, the switching signals of the outgoing phase are fully turned off to restrict the extended tail current, and the torque error of the outgoing phase is compensated by the incoming phase. The proposed modified TSF control scheme is verified by the computer simulations with 30,000[rpm] high speed 4/2 SRM. The simulation and experimental results show the effectiveness of the proposed control scheme.

• Journal of Power Electronics
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• v.14 no.1
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1207-1216
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• 2015

In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.71-72
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• 2011

This paper presents a novel and direct dead time compensation method of the 3 phase inverter using space vector pulse width modulation(SVPWM) topology. In the turn on time calculation of the effective voltage, the dead time effect is directly compensated according to the current direction of the midium voltage reference. Since the turn on time of the effective voltage vector is affected by the dead time, the loss time is compensated to turn on time of the effective voltage vector. And the dead time is added to the calculated voltage vector switching times according to the current direction. For the more effective compensation, the direction of the midium phase current is considered by the practical direction and voltage drops in the power devices. The proposed method can compensate the dead time which is considered feedback error or direction of middle phase current without coordinate transform in added controller. The proposed dead time compensation scheme is verified by the computer simulation and experiments of 3 phase R L load.

• Journal of Korean Library and Information Science Society
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• v.35 no.4
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• pp.1-21
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• 2004

The purpose of this study is to investigate historical backgrounds, maintenance, revision and application areas of UDC(Universal Decimal Classification) in order to understand current issues of it systematically. Since 1905, n has been extensively developed and is now administered by UDC Consortium(UDCC). UDCC updates MRF(Master Reference File), an electronic form of the UDC schedules, once a year. UDC updates and publishes standard edition extended edition, and abridged edition according to the degrees of notion abridgement, and is available on the web. UDC can be now applicable to collection arrangement, SDI(Selective Dissemination of Information) service, searching subject bibliographies, switching language or subject gateway and metadata on the Internet, and automatic classification.