• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.132-139
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• 2002

This paper describes a supply voltage detector and SRAM write driver circuit which dissipates small power. The supply voltage detector generates high signal when supply voltage is higher than reference voltage, but low signal when supply voltage is lower than reference voltage. The write driver utilizes two same-sized drivers to reduce operating current in the write cycle. In the case of lower supply voltage comparing to Vcc, both drivers are active the same as conventional write driver, while in the case of high Vcc only one of two drivers are active so as to deliver the half of the current. As a result of simulation using 0.6${\mu}{\textrm}{m}$ 3.3v/5v, CMOS model parameter, the proposed SRAM scheme shows a 22.6% power reduction and 12.7% PDP reduction at Vcc=3.3V, compared to the conventional one.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• The Journal of Information Systems
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• v.15 no.3
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• pp.107-129
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• 2006

The purpose of this study is to provide and validate an IT cost model hi which we link among cost center, cost object and flexible cost driver. in order to accomplish this purpose, this study utilizes ethnographic research methodology. At first we develop the cost model where the flexible cost driver is the distribution basis of overhead cost. For each cost driver, unit cost management model is also proposed. Then we employ the structured design methodology to validate the model. Based on the IT Cost requirements of a case company, the IT cost system was designed and developed for its test. The result shows the model we developed in this study is appropriate for managing IT resources and further, can be used as a reference model for calculating chargeback rates of other departments and IT budget of IT department.

• Journal of Industrial Technology
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• v.27 no.B
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• pp.125-128
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• 2007

This paper presents Spectral-Domain optical measurement system using self-fabricated CCD sensor driver. The light source is a high brightness white LED and the detector is a 2048 array typed CCD image sensor. I have fabricated the CCD sensor driver to generate four pulse signals, which are the CCD-driving pulses. Using this Spectral Domain optical measurement system, the distance value between the reference mirror and the sample mirror can be obtained successfully.

• The Journal of Information Technology and Database
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• v.7 no.1
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• pp.42-53
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• 2000

The major goal of this research is to develop an optimal route search algorithm for an intelligent route guidance system, one sub-area of ITS. ITS stands for intelligent Transportation System. ITS offers a fundamental solution to various issues concerning transportation and it will eventually help comfortable and swift moves of drivers by receiving and transmitting information on humans, roads and automobiles. Genetic algorithm, and fuzzy logic are utilized in order to implement the proposed algorithm. Using genetic algorithm, the proposed algorithm searches shortest routes in terms of travel time in consideration of stochastic traffic volume, diverse turn constraints, etc. Then using fuzzy logic, it selects driver-preference optimal route among the candidate routes searched by GA, taking into account various driver's preferences such as difficulty degree of driving and surrounding scenery of road, etc. In order to evaluate this algorithm, a virtual road-traffic network DB with various road attributes is simulated, where the suggested algorithm promptly produces the best route for a driver with reference to his or her preferences.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.6
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• pp.928-934
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• 1998

This paper describes a fully digitalized driver for BLDC motors which is realized by a single chip microprocessor. The speed change can be done by using the signal obtained from the position detecting sensor and adjusting the pulse width at the input channel of power module. In order to establish a speed control system a repetitive control method is adopted to track a periodic refer-ence change in the BLDC motor system. The experimental results show accurate reference track-ing performance under the given periodic reference in the repetitive controller design.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.229-229
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• 2004

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.10
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• pp.1-12
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• 2007

Through this experiment driver's perception were measured. An analysis of the perception measurement result analyzed the subject's obstacle perception response time according to voltage patterns. The difference in the reaction time between men and women was also analyzed. Futhermore, the obstacle perception response time was analyzed according to the rate of the brightness of the headlamp. The relative delay time was analyzed In reference to times when there was no voltage change.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.53-60
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• 2005

This work Proposes and describes an LCD backlight driver IC using a voltage feedback circuit which improves the brightness uniformity. The proposed circuit controls the brightness of a backlight by amplifying of sampling voltage at a lamp. To keep the uniformity of brightness, the circuit has a reference lamp. The output voltage of the reference lamp is supplied commonly to each lamp that reduces a resistance deviation of the lamps. As a result, the proposed circuit shows brightness uniformity improvement of about $40\%$ compared to the conventional ones.