• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.2
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• pp.3-10
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• 2008

The choice of basis for representation of element in $GF(2^m)$ affects the efficiency of a multiplier. Among them, a multiplier using redundant representation efficiently supports trade-off between the area complexity and the time complexity since it can quickly carry out modular reduction. So time of a previous multiplier using redundant representation is faster than time of multiplier using others basis. But, the weakness of one has a upper space complexity compared to multiplier using others basis. In this paper, we propose a new efficient multiplier with consideration that polynomial exponentiation operations are frequently used in cryptographic hardwares. The proposed multiplier is suitable fer left-to-right exponentiation environment and provides efficiency between time and area complexity. And so, it has both time delay of $T_A+({\lceil}{\log}_2m{\rceil})T_x$ and area complexity of (2m-1)(m+s). As a result, the proposed multiplier reduces $2(ms+s^2)$ compared to the previous multiplier using equally-spaced polynomials in area complexity. In addition, it reduces $T_A+({\lceil}{\log}_2m+s{\rceil})T_x$ to $T_A+({\lceil}{\log}_2m{\rceil})T_x$ in the time complexity.($T_A$:Time delay of one AND gate, $T_x$:Time delay of one XOR gate, m:Degree of equally spaced irreducible polynomial, s:spacing factor)

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.28-35
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• 2015

In this paper, we propose to identify redundant power states of high-level power model based on clock gating enable signals(CGENs) using dependencies of Boolean functions and structural dependencies of clock gating cells. Three functional dependencies between two CGENs, namely equvalence, inversion, and inclusion, are used. Functions of CGENs in a circuit are represented by binary decision diagrams (BDDs) and the functional relations are used to reduce the number of power states. The structural dependency appears when a clock gating cell drives another clock gating cells in a circuit. Automatic dependency checking algorithm has been proposed. The experimental results show the average number of power state is reduced by 59%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1013-1021
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• 2020

Malware Authorship Attribution is a research field for identifying malware by comparing the author characteristics of unknown malware with the characteristics of known malware authors. The authorship attribution method using binaries has the advantage that it is easy to collect and analyze targeted malicious codes, but the scope of using features is limited compared to the method using source code. This limitation has the disadvantage that accuracy decreases for a large number of authors. This study proposes a method of 'Defining semantic features from binaries' and 'Defining allowable ranges for redundant features using the concept of survival network' to complement the limitations in the identification of binary authors. The proposed method defines Opcode-based graph features from binary information, and defines the allowable range for selecting unique features for each author using the concept of a survival network. Through this, it was possible to define the feature definition and feature selection method for each author as a single technology, and through the experiment, it was confirmed that it was possible to derive the same level of accuracy as the source code-based analysis with an improvement of 5.0% accuracy compared to the previous study.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.4
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• pp.17-22
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• 1974

In this paper, the problem of finding tests to detect faults in combinational logic circuits is considered. At first, the method of fault detection in fan-out-free irredundant circuits is derived, and the result is extended to the fan-out redundant circuits. A fan-out circuit is decomposed into a set of fan-out-free subcircuits by cutting the lines at the internal fan-out points, and the minimal detecting test. sets for each subcircuit are found separately. And then, the compatible tests from each test set are combined maximally into composite tests to generate primary input binary vectors. By this procedure. the minimal complete test sets for reconvergent fan-out circuits are easily found and the detectable and undetectable faults are also classified clearly.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.4
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• pp.43-51
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• 1984

In the case of Quine Mccluskey's methode for Boolean function minimization, we have to examine each bits of binary represented minterms. In this paper, cube relations between misterms that are represented by means of decimal number, and all sorts of rules for Boolean function minimization are described as theorems, and they are verified. And based on these theorems, the new fast algorithm for Boolean function minimization is proposed. An example of manual operation is sholvn, and the process is writed out by a FORTRAN program. In this program, the essential pl.imp implicants of the Boolean function that has 100 each of minterms including redundant minterms, are finked and printed out, (the more minterms can be treated if we take the more larger size of arrays) and the outputs are coincided with the results of manual operation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.4
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• pp.1448-1463
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• 2021

With the continuous development of cloud storage, plenty of redundant data exists in cloud storage, especially multimedia data such as images and videos. Data deduplication is a data reduction technology that significantly reduces storage requirements and increases bandwidth efficiency. To ensure data security, users typically encrypt data before uploading it. However, there is a contradiction between data encryption and deduplication. Existing deduplication methods for regular files cannot be applied to image deduplication because images need to be detected based on visual content. In this paper, we propose a secure image deduplication scheme based on hashing and clustering, which combines a novel perceptual hash algorithm based on Local Binary Pattern. In this scheme, the hash value of the image is used as the fingerprint to perform deduplication, and the image is transmitted in an encrypted form. Images are clustered to reduce the time complexity of deduplication. The proposed scheme can ensure the security of images and improve deduplication accuracy. The comparison with other image deduplication schemes demonstrates that our scheme has somewhat better performance.

• Journal of IKEEE
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• v.26 no.2
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• pp.240-248
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• 2022

Floating-point images that express pixel information as real numbers are used in HDR images. There have been various researches on efficient median filter algorithms, but most of them are applicable to 8-bit depth images and there are only a few number of algorithms applicable to floating-point images, including Gil and Werman's algorithm. In this paper, we propose a median filter algorithm that works efficiently on floating-point images by improving Kim's algorithm, which improved Gil and Werman's algorithm. Experimental results show that the execution time is improved by about 10% compared to the Kim's algorithm by reducing the redundant work for the repetitively used binary search tree and applying the inverted index.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2006.06a
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• pp.351-355
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• 2006

RSA 암호 시스템은 IC카드, 모바일 및 WPKI, 전자화폐, SET, SSL 시스템 등에 많이 사용된다. RSA는 모듈러 지수승 연산을 통하여 수행되며, Montgomery 곱셈기를 사용하는 것이 효율적이라고 알려져 있다. Montgomery 곱셈기에서 임계 경로 지연 시간(Critical Path Delay)은 세 피연산자의 덧셈에 의존하고 캐리 전파를 효율적으로 처리하는 문제는 Montgomery 곱셈기의 효율성에 큰 영향을 미친다. 최근 캐리 전파를 제거하는 방법으로 캐리 저장 덧셈기(Carry Save Adder, CSA)를 사용하는 연구가 계속 되고 있다. McIvor외 세 명은 지수승 연산에 최적인 CSA 3단계로 구성된 Montgomery 곱셈기와 CSA 2단계로 구성된 Montgomery 곱셈기를 제안했다. 시간 복잡도 측면에서 후자는 전자에 비해 효율적이다. 본 논문에서는 후자보다 빠른 연산을 수행하기 위해 캐리 전파 제거 특성을 가진 이진 부호 자리(Signed-Digit, SD) 수 체계를 사용한다. 두 이진 SD 수의 덧셈을 수행하는 잉여 이진 덧셈기(Redundant Binary Adder, RBA)를 새로 제안하고 Montgomery 곱셈기에 적용한다. 기존의 RBA에서 사용하는 이진 SD 덧셈 규칙 대신 새로운 덧셈 규칙을 제안하고 삼성 STD130 $0.18{\mu}m$ 1.8V 표준 셀 라이브러리에서 지원하는 게이트들을 사용하여 설계하고 시뮬레이션 하였다. 그 결과 McIvor의 2 방법과 기존의 RBA보다 최소 12.46%의 속도 향상을 보였다.

• Journal of Communications and Networks
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• v.18 no.2
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• pp.218-226
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• 2016

Coordination among users is an inevitable but time-consuming operation in wireless networks. It severely limit the system performance when the data rate is high. We present FC-MAC, a novel MAC protocol that can complete a contention within one contention slot over a joint frequency-code domain. When a node takes part in the contention, it generates randomly a contention vector (CV), which is a binary sequence of length equal to the number of available orthogonal frequency division multiplexing (OFDM) subcarriers. In FC-MAC, different user is assigned with a distinct signature (i.e., PN sequence). A node sends the signature at specific subcarriers and uses the sequence of the ON/OFF states of all subcarriers to indicate the chosen CV. Meanwhile, every node uses the redundant antennas to detect the CVs of other nodes. The node with the minimum CV becomes the winner. The experimental results show that, the collision probability of FC-MAC is as low as 0.05% when the network has 100 nodes. In comparison with IEEE 802.11, contention time is reduced by 50-80% and the throughput gain is up to 200%.