• Proceedings of the Korean Geotechical Society Conference
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• 2001.03a
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• pp.299-306
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• 2001

Crushed Stone Pile(CSP) is one of the ground improvement methods available to loose sand and clayey ground by forming compacted CSP in the weak soil layer. The effects of this method are enhancement of ground bearing capacity, reduction of settlement and prevention of lateral ground movement in cohesive layer, reduction of liquefaction potential in sandy ground. This study performs model tests in 1.0m${\times}$1.0m${\times}$1.0m and 1.5m${\times}$1.5m${\times}$l.2m model tank to observe bearing capacity of CSP treated ground. The area replacement ratio of CSP composite ground varies 20%, 30% and 40% with square grid pattern. After the composite ground was consolidated under pressure of 0.5kg/$\textrm{cm}^2$ and 1.0kg/$\textrm{cm}^2$, load tests were carried out. The results show that ultimate bearing capacity increases with area replacement ratio and the preconsolidation pressure of ground.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.316-319
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• 1998

RPWM(Random Pulse Width Modulation) is a switching technique to spread the voltage and current harmonics on the wide frequency area. Using randomly changed switching frequency of the inverter, the power spectrum of the electromagnetic acoustic noise cab be spread to the wide-band area. The wide-band noise is much more comfortable and less annoying than the narrow-band one. So RPWM have been attracting an interest as an excellent method for the reduction of acoustic noise on the inverter drive system. In this paper a new RPPWM (Random Position PWM) is proposed and implemented. Each of three pulses is located randomly in each switching interval. Along with the randomization of PWM pulses, the space vector modulation is executed in the C167 microcontroller also. The experimental results show that the voltage and current harmonics were spread to wide band area and that the audible switching noise was reduced by proposed RPPWM method.

• Journal of IKEEE
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• v.19 no.2
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• pp.271-275
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• 2015

This paper proposes a unified HEVC $4{\times}4$ IDCT/IDST architecture for area reduction. In general, $4{\times}4$ IDCT and $4{\times}4$ IDST blocks are implemented separately, and they are connected with multiplexers. In the proposed arechitecture, these two blocks are unified, and internal hardware resources such as multipliers are shared. This reduces the chip area. The synthesized block in 0.18 um technology is 2,795 gates, and the gate count is reduced by 9.44% in comparison with conventional designs.

• Agribusiness and Information Management
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• v.4 no.1
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• pp.1-12
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• 2012

Cameroon, with her numerous resources, still depends on foreign aid while the rate of poverty remains high. Thus, even though historical evidence gives impetus to the impasse over role of developmental aid, from the top down approach through to development as a springboard raising states from the doldrums of poverty, it is still very difficult to draw a substantial relationship between developmental aid and poverty reduction. Against this backdrop of controversy, I find it apt to put Cameroon on a balance scale. Therefore, the purpose of this research is to critically assess the implications of developmental aid on poverty reduction and agro-rural development in Cameroon, using the RUMPI Area Development Project in the South West region of Cameroon as a case study. The study will situate and contextualize the top-down and bottom-up approaches to development within the basis of a Cameroonian perspective, using the Sachs-Easterly debate. The RUMPI Project was introduced with the objective of improving agriculture and empowering the rural woman; thereby fighting poverty within the South West region of Cameroon. Despite its criticism of the barriers to development created by corruption, political pressure and limited use of local and grass-root partnerships, the study, in assessing these failures also tries to outline vital ways in which the project can be improved upon.

• Journal of Korean Society of Water and Wastewater
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• v.26 no.6
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• pp.735-745
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• 2012

Storage method is one of major measures for reduction of CSOs pollutant loads and several projects have been done nationwide. But systematic analysis of intercepting capacity has not been studied to determine optimum size of storage facility. In this research, not only storage volume but also intercepting capacity which means flow capacity from intercepting facility to CSOs storage facility was studied and optimum sizing method for storage facility was proposed. The result shows that pollutants reduction efficiency can be increased significantly by increasing intercepting capacity and it might reduce storage volume and total construction costs. Intercepting capacity for the study area was evaluated and it was shown as equivalent to 83 % probability rainfall intensity.

• Journal of electromagnetic engineering and science
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• v.17 no.3
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• pp.153-158
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• 2017

This work reports on the effect of plasma area on the frequency characteristics of the monostatic radar cross section (RCS) of a square metallic plate. A dielectric barrier discharge (DBD) plasma actuator consisting of 10 rings is proposed. The actuator is fabricated in three different configurations such that only three inner rings, seven inner rings, and all rings can be biased. By applying an 18-kV bias at 1 kHz, the three types of DBD actuators generate plasma with a total area of 16.96, 36.74, and $53.69cm^2$, respectively, in a ring or circular form. The experimental results reveal that when the DBD actuator is placed in front of a $20mm{\times}20cm$ conducting plate, the monostatic RCS is reduced by as much as 18.5 dB in the range of 9.41-11.65 GHz. Furthermore, by generating the plasma and changing the area, the frequency of maximum reduction in the monostatic RCS of the plate can be controlled. The frequency is reduced by nearly 20% in the X band when all rings are biased. Finally, an electromagnetic model of the plasma is obtained by comparing the experimental and full-wave simulated results.

• Korean Journal of Hydrosciences
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• v.7
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• pp.21-35
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• 1996

This Study is to develop the suitable hydrologic models for determination of the size and location of detention storage facilities to restrain stormwater runoff in urban areas. Hypothetical areas of two levels are considered to seize the hydrologic response characteristics. A one-square-kilometer ares is selected for the catchment level, and a 10-square-kilometer area consisting of 10 catchments is adapted at the watershed level as representative of urban drainage area. In this analysis, different rainfall freqyencies, land uses, drainage patte군, basin shates and detention storage policies are considered. Folw reduction effect of detention storage facilities is deduced from storage ratio and detention basin factor. A substantial saving in detention storage volumes is achieved 노두 the detention storage is planned at the watershed level rather than the catchment level. For the application of real watersheds, two watersheds in Seoul metropolitan area-Jamshil 2 and Seongnae 1-are selected on the basis of hydrologic response charactaristics. Through the regression analysis between dimensionless deterntion storage volume, dimensionless upstream area ratio and reduction rate of storage ratio, the regression equations to determine the size and location of detention storage faclities are presented.

• Proceedings of the Korean Society of Soil and Groundwater Environment Conference
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• 1999.04a
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• pp.62-63
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• 1999

Reduction 2,4,6-Trinitrotoluene by zero valent iron was studied in a batch reactor under anoxic conditions. Results showed that the removal of TNT was a pseudo-first order and the rate was dependent on the available metal surface area. Final product, presumably triaminotoluene, accumulated in the solution as well as on the metal surface. However, little amounts of aminodinitrotoluenes were detected. Therefore, it is postulated that the reduction of nitro group occurs simultaneously in all three position.

• Proceedings of the Korean Society of Soil and Groundwater Environment Conference
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• 2000.05a
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• pp.108-111
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• 2000

FeS/FeS$_2$ minerals have been known to be potentially useful reductant to the removal of common organic contaminants in groundwater and soil. This research is aimed at improving our understanding of factors affecting the pathways and rates of reductive transformation of Hexachloroethane by catalytical iron minerals in natural system. Hexachloroethane is reduced by FeS/FeS$_2$ minerals under anaerobic condition to tetrachloroethylene and trichloroethylene with pentachloroethyl radical as the intermediate products. The kinetics of reductive transformations of the Hexachloroethane have been investigated in aqueous solution containing FeS, FeS$_2$. The proposed reduction mechanism for the adsorbed nitrobenzene involves the electron donor-acceptor complex as a precursor to electron transfer. The adsorbed Hexachloroethane undergo a series of electron transfer, proton transfer and dehydration to achieve complete reduction. It can be concluded that the reductive transformation reaction takes place at surface of iron-bearing minerals and is dependent on surface area and pH. Nitrobenzene reduction kinetics is affected by reductant type, surface area, pH, the surface site density, and the surface charge. FeS/FeS$_2$-mediated reductive dechlorination may be an important transformation pathway in natural systems.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.270-276
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• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.