• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.83-90
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• 1998

The effects of dopant activation anneal on GOI (Gate Oxide Integrity) of MOS capacitor with amorphous silicon gate electrode were investigated. It was found that the amorphous silicon gate electrode was crystallized and the dopant atoms were sufficiently activated by activation anneal. The mechanical stress of gate electrode that reveals large compressive stress in amorphous state, was released with increase of anneal temperature from $700^{\circ}C$ to 90$0^{\circ}C$. The resistivity of gate electrode polycrystalline silicon film is decreased by the increase of anneal temperature. The reliability of thin gate oxide and interface properties between oxide and silicon substrate greatly depends on the activation anneal temperature. The charge trapping characteristics as well as oxide reliability are improved by the anneal of 90$0^{\circ}C$ compare to that of $700^{\circ}C$ or 80$0^{\circ}C$. Especially, the lifetimes of the thin gate oxide estimated by TDDB method is 3$\times$10$^{10}$ for the case of $700^{\circ}C$ anneal, is significantly increased to 2$\times$10$^{12}$ for the case of 90$0^{\circ}C$ anneal. Finally, the interface trap density is reduced with relaxation of mechanical stress of gate electrode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.9
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• pp.916-923
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• 2004

In this paper, the strained Si$_{0.9}$Ge$_{0.1}$ epitaxial layers grown by a reduced pressure chemical vapor deposition (RPCVD) on Si (100) were characterized by Rutherford backscattering spectrometery (RBS) for the fabrication of an SiGe heterojunction bipolar transistor(HBT). RBS spectra of the ${Si}_0.9{Ge}_0.1$epitaxial layers grown on the Si substrates which were implanted with the phosphorus (P) ion and annealed at a temperature between $850^{\circ}C$ - $1000^{\circ}C$ for 30min were analyzed to investigate the post thermal annealing effect on the grown${Si}_0.9{Ge}_0.1$epitaxial layer quality. Although a damage of the substrates by P ion-implantation might be cause of the increase of RBS yield ratios, but any defects such as dislocation or stacking fault in the grown ${Si}_0.9{Ge}_0.1$ epitaxial layer were not found in transmission electron microscope (TEM) photographs. The post high temperature rapid thermal annealing (RTA) effects on the crystalline quality of the ${Si}_0.9{Ge}_0.1$ epitaxial layers were also analyzed by RBS. The changes in the RBS yield ratios were negligible for RTA a temperature between $900^{\circ}C$ - $1000^{\circ}C$for 20 sec, or $950^{\circ}C$for 20 sec - 60 sec. A SiGe HBT array shows a good Gummel characteristics with post RTA at $950^{\circ}C$ for 20 sec.sec.sec.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.