• Title/Summary/Keyword: Reconfigurable Structure

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Digital Circuit Synthesis on FPGA by using Genetic Algorithm (유전자알고리즘을 이용한 FPGA에서의 디지털 회로의 합성)

  • Park, Tae-Suh;Wee, Jae-Woo;Lee, Chong-Ho
    • Proceedings of the KIEE Conference
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    • 1999.07g
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    • pp.2944-2946
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    • 1999
  • In this paper, digital circuit evolution is proposed as an intrinsic evolvable system. Evolutionary hardware is a reconfigurable one which adapt itself to the environment and evolve its structure to realize desired performance. By using special FPGA and genetic algorithm, we have made a prototype of intrinsic hardware evolution system. As an example for digital circuit evolution, full adder realization is performed. As the result of this, a very complex structure of digital circuit performing full adder was created. Analysis made on the hardware revealed that some undetermined circuits were developed.

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Expansible & Reconfigurable Neuro Informatics Engine : ERNIE (대규모 확장이 가능한 범용 신경망 연산기 : ERNIE)

  • 김영주;동성수;이종호
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.40 no.6
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    • pp.56-68
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    • 2003
  • Difficult problems In implementing digital neural network hardware are the extension of synapses and the programmability for relocating neurons. In this paper, the structure of a new hardware is proposed for solving these problems. Our structure based on traditional SIMD can be dynamically and easily reconfigured connections of network without synthesizing and mapping original design for each use. Using additional modular processing unit the numbers of neurons find synapses increase. To show the extensibility of our structure, various models of neural networks : multi-layer perceptrons and Kohonen network are formed and tested. The performance comparison with software simulation shows its superiority in the aspects of performance and flexibility.

A decentralized approach to damage localization through smart wireless sensors

  • Jeong, Min-Joong;Koh, Bong-Hwan
    • Smart Structures and Systems
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    • v.5 no.1
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    • pp.43-54
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    • 2009
  • This study introduces a novel approach for locating damage in a structure using wireless sensor system with local level computational capability to alleviate data traffic load on the centralized computation. Smart wireless sensor systems, capable of iterative damage-searching, mimic an optimization process in a decentralized way. The proposed algorithm tries to detect damage in a structure by monitoring abnormal increases in strain measurements from a group of wireless sensors. Initially, this clustering technique provides a reasonably effective sensor placement within a structure. Sensor clustering also assigns a certain number of master sensors in each cluster so that they can constantly monitor the structural health of a structure. By adopting a voting system, a group of wireless sensors iteratively forages for a damage location as they can be activated as needed. Since all of the damage searching process occurs within a small group of wireless sensors, no global control or data traffic to a central system is required. Numerical simulation demonstrates that the newly developed searching algorithm implemented on wireless sensors successfully localizes stiffness damage in a plate through the local level reconfigurable function of smart sensors.

Pattern-Switchable Microstrip Patch Antenna with Loop Structure (패턴 변환 루프 구조를 가지는 마이크로스트립 패치 안테나)

  • Kim, Yongjin
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.11
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    • pp.5447-5451
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    • 2012
  • This paper presents a pattern-switchable microstrip patch antenna with loop structure. The loop structure for switchable radiation beam pattern is connected with feeding line of the microstrip patch antenna. As changing switch on/off state, the radiation beam pattern can be changed. The target frequency is 2.4 GHz and maximum radiation gain is 3.2dBi. The proposed antenna is useful for diversity antenna and smart antenna in modern wireless communication including MIMO (Multi-Input Multi-Output) and WLAN system. The sizes of the rectangular patch and the ground plane are $28mm{\times}28mm$ and $40mm{\times}50mm$, respectively. The simulation and experimental results show that the antenna radiation pattern can be changed with switch on/off configuration.

Ambient Intelligence in Distributed Modular Systems

  • Ngo Trung Dung;Lund Henrik Hautop
    • Proceedings of the IEEK Conference
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    • summer
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    • pp.421-426
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    • 2004
  • Analyzing adaptive possibilities of agents in multi-agents system, we have discovered new aspects of ambient intelligence in distributed modular systems using intelligent building blocks (I-BLOCKS) [1]. This paper describes early scientific researches related to technical design, applicable experiments and evaluation of adaptive processing and information interaction among I-BLOCKS allowing users to easily develop ambient intelligence applications. The processing technology presented in this paper is embedded inside each DUPLO1 brick by microprocessor as well as selected sensors and actuators in addition. Behaviors of an I-BLOCKS modular structure are defined by the internal processing functionality of each I-Blocks in such structure and communication capacities between I-BLOCKS. Users of the I-BLOCKS system can do 'programming by building' and thereby create specific functionalities of a modular structure of intelligent artefacts without the need to learn and use traditional programming language. From investigating different effects of modem artificial intelligence, I-BLOCKS we have developed might possibly contain potential possibilities for developing applications in ambient intelligence (AmI) environments. To illustrate these possibilities, the paper presents a range of different experimental scenarios in which I-BLOCKS have been used to set-up reconfigurable modular systems. The paper also reports briefly about earlier experiments of I-BLOCKS in different research fields, allowing users to construct AmI applications by a just defined concept of modular artefacts [3].

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Proposal and Implementation of 2-D OCDMA System with Reconfigurable Array Encoder/Decoder and Double Hard Limiters (배열형 가변 부호기/복호기와 이중 하드 리미터를 적용한 2-D OCDMA시스템 제안 및 구현)

  • 김진석;김범주;권순영;박종대
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.7A
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    • pp.705-711
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    • 2004
  • We propose novel OCDMA system with the structure of reconfigurable may encoder/decoder(RAE/ RAD), which are able to reallocate the 2-D optical codes to each subscriber and recover the transmitted data at all the receiving nodes. We have first implemented the double hard limiters composed of limiting amplifier(first hard limiter) that maintain a level of the encoded data from receiving node and AND detector(second hard limiter) for detecting the position of the encoded data and recovering the data. With the proposed system, it was successfully implemented to recover a specific channel data out of 16 code-multiplxed channels using FPGA and 4 DFB-LDs having distinct wavelengths. From experimental results, the code length resulted from increasing the number of the simultaneously connected channels has been reduced by using 2-D OCDMA multiplexed in time and wavelength instead of 1-D OCDMA. In addition, bit errors phenomenon on account of deterioration of autocorrelation peak-to-side lobe ratio is enhanced by using the double hard limiters composed of AND detector and limiting amplifiers.

Dual-Band Frequency Reconfigurable Small Eighth-Mode Substrate-Integrated Waveguide Antenna (이중 대역 주파수 가변 1/8차 소형 기판집적형 도파관 안테나)

  • Kang, Hyunseong;Lim, Sungjoon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.1
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    • pp.10-18
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    • 2014
  • In this paper, we propose a new frequency reconfigurable dual-band antenna. By using an electronically compact eighth-mode substrate-integrated-waveguide(EMSIW) resonator, we have designed a compact antenna, which performs dual-band movement by additionally loading a complementary split ring resonator(CSRR) structure. The EMSIW and CSRR structures are designed to satisfy the bandwidths of 1.575 GHz(GPS) and 2.4 GHz(WLAN), respectively. We load the CSRR with a varactor diode to allow a narrow bandwidth and to enable the resonance frequency to continuously vary from 2.4 GHz to 2.5 GHz. Thus, we realize a channel selection function that is used in the WLAN standards. Irrespective of how a varactor diode moves, the EMSIW independently resonates so that the antenna maintains a fixed frequency of the GPS bandwidth even at different voltages. Consequently, as the DC bias voltage changes from 11.4 V to 30 V, the resonance frequency of the WLAN bandwidth continuously changes between 2.38 GHz and 2.5 GHz, when the DC bias voltage changes from 11.4 V to 30 V. We observe that the simulated and the measured S-parameter values and radiation patterns are in good agreement with each other.

Design of 4th Order ΣΔ modulator employing a low power reconfigurable operational amplifier (전력절감용 재구성 연산증폭기를 사용한 4차 델타-시그마 변조기 설계)

  • Lee, Dong-Hyun;Yoon, Kwang-Sub
    • Journal of IKEEE
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    • v.22 no.4
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    • pp.1025-1030
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    • 2018
  • The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.

A Study on Multimedia Processor Architecture (멀티미디어 프로세서 아키텍쳐에 관한 연구)

  • Park, Chun-Myoung;Lee, Taek-Keun
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.1177-1180
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    • 2005
  • This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

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Cooperative Coordination Method of Neural Network Controller Module for Autonomous Mobile Robot Navigation

  • Joo, Han-Seong;Young, Oh-Se
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.178.3-178
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    • 2001
  • This paper is concerned with designing a neural network based navigator that is optimized in a user-defined sense for a mobile robot using ultrasonic sensors to travel to a goal position safely and efficiently without any prior map of the environment. The neural network has a dynamically reconfigurable structure that not only can optimize the weights but also the input sensory connectivity in order to meet any user-defined objective. Therefore, in this research, we can select an optimal subset of sensory inputs that results in the best performance related to both navigation and structural complexity. Further, this research uses the manually trained initial population and the modular neural network to alleviate ...

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