• Title/Summary/Keyword: Reconfigurable Computing

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A RMESH Algorithm for Computing Perimeter of Linear Quadtrees (선형 사진트리의 둘레 길이를 계산하기 위한 RMESH 알고리즘)

  • 김기원;우진운
    • Proceedings of the Korean Information Science Society Conference
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    • 1998.10b
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    • pp.658-660
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    • 1998
  • 계층적 자료구조인 사진트리는 이진 영상을 표현하는데 매우 중요한 자료구조이다. 선형 사진트리는 사진트리를 메모리에 저장하는데 매우 효율적이므로 사진트리와 관련된 연산의 수행을 위해 많은 연구가 진행되어 왔다. 본 논문에서는 RMESH(Reconfigurable MESH) 구조에서 3-차원 n$\times$n$\times$n 프로세서를 사용하여 선형 사진트리로 표현된 이진 영상의 둘레 길이를 계산하는 상수 시간 알고리즘을 제안한다.

Development of a SAD Correlater for Real-time Stereo Vision (실시간 스테레오 비젼 시스템을 위한 SAD 정합연산기 설계)

  • Yi, Jong-Su;Yang, Seung-Gu;Kim, Jun-Seong
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.45 no.1
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    • pp.55-61
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    • 2008
  • A real-time three-dimensional vision is a passive system, which would support various applications including collision avoidance, home networks. It is a good alternative of active systems, which are subject to interference in noisy environments. In this paper, we designed a SAD correlator with respect to resource usage for a real-time three-dimensional vision system. Regular structures, linear data flow and abundant parallelism make the correlation algorithm a good candidate for a reconfigurable hardware. We implemented two versions of SAD correlator in HDL and synthesized them to determine resource requirements and performance. From the experiment we show that the SAD correlator fits into reconfigurable hardware in marginal cost and can handle about 30 frames/sec with $640{\times}480$ images.

Efficient Token Flow Design for the MPEG RMC Framework

  • Cui, Li;Kim, Sowon;Kim, Hyungyu;Jang, Euee S.
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.5
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    • pp.251-258
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    • 2014
  • This paper proposes an efficient token flow design methodology for a decoder in the MPEG Reconfigurable Media Coding (RMC) framework. The MPEG RMC framework facilitates a decoder to be configured with a set of modules called functional units (FUs) that are connected by tokens. Such a modular design philosophy of the MPEG RMC framework enables the reusability and reconfigurability of FUs. One drawback of the MPEG RMC framework is that the decoder performance can be affected by increasing the token transmissions between FUs. The proposed method improves the design of the FU network in the RMC framework toward real-time decoder implementation. In the proposed method, the merging of FU, the separation of token flow, and the merging of token transactions are applied to minimize the token traffic between FUs. The experimental results of the MPEG-4 SP decoder show that the proposed method reduces the total decoding time by up to 77 percent compared to the design of the RMC simulation model.

Simulator for Dynamic 2/3-Dimensional Switching of Computing Resources

  • Ki, Jang-Geun;Kwon, Kee-Young
    • International Journal of Internet, Broadcasting and Communication
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    • v.12 no.3
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    • pp.9-17
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    • 2020
  • In this paper, as part of the research for the infrastructure of very high flexible and reconfigurable data center using very high speed crossbar switches, we developed a simulator that can model two and three dimensional connection structure of switches with an efficient control algorithm using software defined network and verified the functions and analyzed the performance accordingly. The simulator consists of a control module and a switch module that was coded using Python language based on the Mininet and Ryu Openflow frameworks. The control module dynamically controls the operation of switching cells using a shortest multipath algorithm to calculate efficient paths adaptively between configurable computing resources. Performance analysis by using the simulator shows that the three-dimensional switch architecture can accommodate more hosts per port and has about 1.5 times more successful 1:n connections per port with the same number of switches than the two-dimensional architecture. Also simulation results show that connection length in a 3-dimensional way is shorter than that of 2-dimensional way and the unused switch ratio in a 3-dimensional case is lower than that of 2-dimensional cases.

Constant Time RMESH Algorithm for Computing Area and Perimeter of Binary Image Represented by Linear Quadtrees (선형 사진트리로 표현된 이진 영상의 면적과 둘레 길이를 계산하기 위한 상수시간 RMESH 알고리즘)

  • Kim, Gi-Won;U, Jin-Un
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.7
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    • pp.1746-1758
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    • 1998
  • 계층적 자료구조인 사진트리는 이진 영상을 표현하는데 매우 중요한 자료구조이다. 사진트리를 메모리에 저장하는 방법중 선형 사진트리 표현 방법은 다른 표현 방법과 비교할 때 저장 공간을 매우 효율적으로 절약할 수 있는 이점이 있기 때문에 사진트리와 관련된 연산의 수행을 위해 선형 사진트리를 사용하는 효율적인 알고리즘 개발에 많은 연구가 진행되어 왔다. 본 논문에서는 REMSH(Reconfigurable MESH) 구조에서 3-차원 n$\times$n$\times$n 프로세서를 사용하여 선형 사진트리로 표현된 이진 영상의 면적과 둘레 길이를 계산하는 알고리즘을 제안한다. 이 알고리즘은 0(1) 시간 복잡도를 갖는다.

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A review on several methods for fast generation of digital Fresnel holograms

  • Tsang, P.W.M.
    • Journal of Korea Society of Industrial Information Systems
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    • v.17 no.2
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    • pp.29-32
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    • 2012
  • Computer generated holography (CGH) is technology for generating holograms of synthetic, three dimensional (3D) objects which may not exist in the physical world. The process, however, requires heavy amount of computation as the resolution of a hologram is significantly higher than that of a typical optical image. This paper reviews four modern techniques for fast generation of digital Fresnel holograms which are important in the development of holographic video systems. The methods that will be described include the virtual window, sub-line, wavefront recording plane (WRP), and the interpolative WRP schemes. These works share the common objective to generate digital Fresnel hologram at a speed that is close to the video frame rate, and with complexity which is realizable with affordable computing and reconfigurable hardware devices. The author will present the principles and realization of these works, as well as some potential area of research in digital holography.

Cloud Radio Access Network: Virtualizing Wireless Access for Dense Heterogeneous Systems

  • Simeone, Osvaldo;Maeder, Andreas;Peng, Mugen;Sahin, Onur;Yu, Wei
    • Journal of Communications and Networks
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    • v.18 no.2
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    • pp.135-149
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    • 2016
  • Cloud radio access network (C-RAN) refers to the virtualization of base station functionalities by means of cloud computing. This results in a novel cellular architecture in which low-cost wireless access points, known as radio units or remote radio heads, are centrally managed by a reconfigurable centralized "cloud", or central, unit. C-RAN allows operators to reduce the capital and operating expenses needed to deploy and maintain dense heterogeneous networks. This critical advantage, along with spectral efficiency, statistical multiplexing and load balancing gains, make C-RAN well positioned to be one of the key technologies in the development of 5G systems. In this paper, a succinct overview is presented regarding the state of the art on the research on C-RAN with emphasis on fronthaul compression, baseband processing, medium access control, resource allocation, system-level considerations and standardization efforts.

A Parallel Algorithm for Finding Routes in Cities with Diagonal Streets

  • Hatem M. El-Boghdadi
    • International Journal of Computer Science & Network Security
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    • v.24 no.1
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    • pp.45-51
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    • 2024
  • The subject of navigation has drawn a large interest in the last few years. The navigation within a city is to find the path between two points, source location and destination location. In many cities, solving the routing problem is very essential as to find the route between different locations (starting location (source) and an ending location (destination)) in a fast and efficient way. This paper considers streets with diagonal streets. Such streets pose a problem in determining the directions of the route to be followed. The paper presents a solution for the path planning using the reconfigurable mesh (R-Mesh). R-Mesh is a parallel platform that has very fast solutions to many problems and can be deployed in moving vehicles and moving robots. This paper presents a solution that is very fast in computing the routes.

Variability Support in Component-based Product Lines using Component Code Generation (컴포넌트 코드 생성을 통한 컴포넌트 기반 제품 라인에서의 가변성 지원)

  • Choi, Seung-Hoon
    • Journal of Internet Computing and Services
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    • v.6 no.4
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    • pp.21-35
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    • 2005
  • Software product-lines is the software development paradigm to attain the rapid development of quality applications by customizing the reconfigurable components and composing them based on predefined software architectures. Recently various methodologies for the component-based product lines are proposed, but these don't provide the specific implementation techniques of the components in terms of variability resolution mechanism. In other hand, the several approaches to implement the component supporting the variabilities resolution are developed, but these don't define the systematic analysis and design method considering the variabilities from the initial phase. This paper proposes the integration of PLUS, the one of product line methodologies extending UML modeling, and component code generation technique in order to increase the efficiency of producing the specific product in the software product lines. In this paper, the component has the hierarchical architecture consisting of the implementation elements, and each implementation elements are implemented as XSLT scripts. The codes of the components are generated from the feature selection. Using the microwave oven product lines as case study, the development process for the reconfigurable components supporting the automatic variability resolution is described.

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Constant Time Algorithm for Computing Block Location of Linear Quadtree on RMESH (RMESH에서 선형 사진트리의 블록 위치 계산을 위한 상수시간 알고리즘)

  • Han, Seon-Mi;Woo, Jin-Woon
    • The KIPS Transactions:PartA
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    • v.14A no.3 s.107
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    • pp.151-158
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    • 2007
  • Quadtree, which is a hierarchical data structure, is a very important data structure to represent images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The computation of block location is one of important geometry operations in image processing, which extracts a component completely including a given block. In this paper, we present a constant time algorithm to compute the block location of images represented by quadtrees, using three-dimensional $n\times n\times n$ processors on RMESH(Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to deal with the locational codes of quardtree on the hierarchical structure of $n\times n\times n$ RMESH.