• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.139-144
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• 1998

This paper describes the design of a variable rate QPSK demodulator for digital satellite TV system. This true variable-rate demodulator employs a unique architecture to realize an all digital synchronization and detection algorithm. Data-flow based design approach enabled a seamless transition from high level design optimization to physical layout. The demodulator has been integrated with Viterbi decoder, de-interleaver, and Ree-Solomon decoder to make a single chip Digital Video Broadcast (DVB) receiver. The receiver IC has been fabricated with a 0.5mm CMOS TLM process and proved fully functional in a real-world set-up.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.1011-1012
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• 2006

In this paper, implementation process of standard platform for T-DMB Receiver in low-cost and small-size are following: First, implement SoC for 32 bit RISC CPU and 16 bit DSP, Hardware H.264 CODEC, Post Processor or Video Display, Audio Processor, I/O Device. Second, implement Real Time OS for flexible application. Third, propose simple architecture for interface with peripheral devices using one-chip processor.

• 한국전자파학회논문지
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• 제19권9호
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• pp.1045-1050
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• 2008

본 논문에서는 IR-UWB 통신에 적합한 저 전력, 저복잡도의 CMOS RF 수신기를 제작하였다. 제안된 IR-UWB 수신기는 비교적 구조가 간단한 non-coherent demodulation 방식으로 설계, 제작되었다. 설계된 IR-UWB 수신기는 LNA, envelop detector, VGA, comparator로 구성되어 있으며, envelop detector, VGA, comparator는 $0.18{\mu}m$ CMOS 공정 기술을 이용하여 단일 칩으로 설계, 제작하였다. 측정 결과 data rate이 1 Mbps일 때 sensitivity가 -70 dBm이며, 이때 BER은 $10^{-3}$의 값을 가진다. 외부의 LNA를 제외한 단일 칩 CMOS IR-UWB 수신기의 전류 소모는 전압이 1.8 V일 때 5 mA이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1358-1361
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• 2002

In this paper, we propose a new architecture of digital automatic gain control (AGC) for a wideband code division multiple access (WCDMA) receiver. The feature of the proposed architecture is simplicity, in that it does not utilize complicated mathematical functions such as log and its inverse. When the proposed algorithm is implemented using a field programmable gate array (FPGA) device, the number of slices used to implement is 130 over the total of 5120 slices (less than 3%) with 61.44 ㎒ clock. This algorithm has been successfully applied to commercial WCDMA base stations.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.394-396
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• 2006

When developing a new GPS receiver module, the essential problems are evaluation of reliable algorithms, software debugging, and performance comparison between algorithms to find optimal solution. Most GPS receiver modules nowadays use a correlator to track signals from satellites and an MCU (Micro Controller Unit) to control operations of the entire module. The problem of software evaluation from MCU is very difficult, due to limitation of MCU resources and low ability of interfacing with user. Normally, user has to expense special tool kit for a limiting access to MCU but it is also hard to use. This article introduces an implementation of a GPS receiver test bed using correlator GP2021 interfacing with ISA (Industry Standard Architecture) PC bus. This way can give user complete control and visibility into the operation of the receiver, then user can easily debug program and test algorithms. For this article, the least square method is implemented to test the hardware and software performance.

• 한국통신학회논문지
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• 제29권9A호
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• pp.1005-1012
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• 2004

본 논문에서는 W-CDMA 단말기 표준안에서 요구하는 최소 성능을 분석하고 현재 상용화되어 있는 부품들을 사용하여 W-CDMA 단말기 수신부를 설계 및 제작하였다 표준안의 테스트 조건들로부터 수신 시스템의 최대 잡음지수와 IIP3 을 도출하였으며, 인접채널에 대한 선택도 및 프콘트 -엔드 단의 최소 성능을 경쟁하였다 제작에 앞 서 ADS 를 이용하여 성능검증을 하였으며 , 모두 분석된 최소성능을 만족하였다. 끝으로 W-CDMA 단말기 수신부 를 헤테로다인 구조로 R 단에서 IF 단까지 제작하였으며, 측정을 하였다 따라서 본 논문이 W-CDMA 단말기를 제작함에 있어 이론적인 설계 기준이 될 것으로 여겨진다.

• 대한원격탐사학회:학술대회논문집
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• 대한원격탐사학회 2002년도 Proceedings of International Symposium on Remote Sensing
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• pp.297-302
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• 2002

The subsystems of two channel correlation radiometer such as RF front-end, IF and LF unit, LO unit, software based I/Q demodulator and complex correlator are characterized and their performance is analyzed in this paper. The limited hardware calibration method and receiver design consideration are discussed. The receiver architecture of 37GHz correlation radiometer is integrated. The designed radiometer employs a single-sideband superheterodyne receiver. The center frequency of the radiometer is 37 GHz and IF center frequency is 1.95 GHz with the equivalent noise bandwidth of 79.6 MHz. The receiver has less than 4.2 dB noise figure which is calculated by the Y-factor method and its gain can be adjusted from 60 dB to 80 dB.

• Journal of Positioning, Navigation, and Timing
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• 제7권4호
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• pp.189-203
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• 2018

In this paper, a Software Defined Radio (SDR) architecture was designed and implemented for rapid prototyping of GNSS receiver. The proposed SDR can receive various GNSS and direct sequence spread spectrum (DSSS) signals without software modification by expanded input parameters containing information of the desired signal. Input parameters include code information, center frequency, message format, etc. To receive various signal by parameter controlling, a correlator, a data bit extractor and a receiver channel were designed considering the expanded input parameters. In navigation signal processing, pseudorange was measured based on Coordinated Universal Time (UTC) and appropriate navigation message decoder was selected by message format of input parameter so that receiver position can be calculated even if SDR is set up various GNSS combination. To validate the proposed SDR, the software was implemented using C++, CUDA C based on GPU and USRP. Experimentation has confirmed that changing the input parameters allows GPS, GLONASS, and BDS satellite signals to be received. The precision of the position from implemented SDR were measured below 5 m (Circular Error Probability; CEP) for all scenarios. This means that the implemented SDR operated normally. The implemented SDR will be used in a variety of fields by allowing prototyping of various GNSS signal only by changing input parameters.

• ETRI Journal
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• 제24권2호
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• pp.161-171
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• 2002

This paper proposes a novel decision feedback differential phase detection (DF-DPD) for M-ary DPSK. A conventional differential phase detection method for M-ary Differential Phase Shift Keying (DPSK) can simplify the receiver architecture. However, it possesses a poorer bit error rate (BER) performance than coherent detection because of the prior noisy phase sample. Multiple-symbol differential detection methods, such as maximum likelihood differential phase detection, Viterbi-DPD, and DF-DPD using L-1 previous detected symbols, have attempted to improve BER performance. As the detection length, L, increases, the BER performance of the DF-DPD improves but the complexity of the architecture increases dramatically. This paper proposes a simplified DF-DPD architecture replacing the conventional delay and additional architecture with an accumulator. The proposed architecture also improves BER performance by minimizing the current differential phase noise through the accumulation of previous differential phase noise samples. The simulation results show that the BER performance of the proposed architecture approaches that of a coherent detection with differential decoding.

• 한국항행학회논문지
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• 제14권3호
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• pp.328-335
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• 2010

본 논문에서는 2개의 송수신 안테나를 갖는 $2{\times}2$ MIMO-OFDM 기반 무선 LAN 기저대역 수신 모뎀을 위한 효율적인 수신 알고리즘 및 면적 효율적인 하드웨어 구조를 제시한다. 수신기 성능향상을 위해 효율적인 시간 동기 알고리즘과 MML 알고리즘 기반 MIMO 심볼 검출기 구조를 제안한다. 또한, 제안된 심볼 검출기는 IEEE 802.11n 무선 LAN 규격에 정의된 대로 MIMO 전송 기법 중 공간 다이버시티 모드뿐 아니라 공간 다중화 모드를 모두 지원하며, 다단 (multi-stage) 파이프라인 구조와 극좌표 형태의 복소수 승산 방법을 사용하여 연산블록의 공유와 연산기의단순화를 진행하였고, 이를 통해 하드웨어 복잡도를 크게 감소시켰다. 제안된 하드웨어 구조는 하드웨어 설계 언어(HDL)를 이용하여 설계 되었고, 0.13um CMOS standard 셀 라이브러리 통해 합성되었다. 그 결과 기존의 설계 구조와 비교시 56% 감소된 하드웨어 복잡도로 구현 가능함을 확인하였다.