• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1380-1386
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• 2009

In this paper, we propose a CQS(Calendar Queue Scheduler) architecture which was designed for processing multimedia and timing traffic in home network. With various characteristics of the increased traffic flowed in home such as VoIP, VOD, IPTV, and Best-efforts traffic, the needs of managing QoS(Quality of Service) are being discussed. Making a group regarding application or service is effective to guarantee successful QoS under the restricted circumstances. The proposed design is aimed for home gateway corresponding to the end points of receiver on end-to-end QoS and eligible for supporting multimedia traffic within restricted network sources and optimizing queue sizes. Then, we simulated the area for each module and each memory. The area for each module is referenced by NAND($2{\times}1$) Gate(11.09) when synthesizing with Magnachip 0.18 CMOS libraries through the Synopsys Design Compiler. We verified the portion of memory is 85.38% of the entire CQS. And each memory size is extracted through CACTI 5.3(a unit in mm2). According to the increase of the memory’sentry, the increment of memory area gradually increases, and defining the day size for 1 year definitely affects the total CQS area. In this paper, we discussed design methodology and operation for each module when designing CQS by hardware.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.5
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• pp.9-20
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• 2005

In this paper, we propose ubiTrack, a system which tracks users' location in indoor environments by employing infrared-based proximity method. Most of recently developed systems have focussed on performance and accuracy. For this reason, they adopted the idea of centralized management, which gathers all information in a main system to monitor users' location. However, these systems raise privacy concerns in ubiquitous computing environments where tons of sensors are seamlessly embedded into environments. In addition, centralized systems also need high computational power to support multiple users. The proposed ubiTrack is designed as a passive mobile architecture to relax privacy problems. Moreover, ubiTrack utilizes appropriate area as a unit to efficiently track users. To achieve this, ubiTrack overlaps each sensing area by utilizing the TDM (Time-Division Multiplexing) method. Additionally, ubiTrack exploits various filtering methods at each receiver and utilization module. The filtering methods minimize unexpected noise effect caused by external shock or intensity weakness of ID signal at the boundary of sensing area. ubiTrack can be applied not only to location-based applications but also to context-aware applications because of its associated module. This module is a part of middleware to support communication between heterogeneous applications or sensors in ubiquitous computing environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1027-1034
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• 2005

IEEE802.15.4a, which is started to realize the PHY layer including high precision ranging/positioning and low data rate communication functions, requires a simple and low power consumable transceiver architecture. To satisfy this requirements, the simple noncoherent on-off keying (OOK) UWB transceiver with the parallel energy window banks (PEWB) giving high precision signal processing interface is proposed. The flexibility of the proposed system in multipath fading channel environments is acquired with the pulse and bit repetition method. To analyze the bit error rate (BER) performance of this proposed system, a noise model in receiver is derived with commonly used random variable distribution, chi-square. BER of $10^{-5}$ under the line-of-sight (LOS) residential channel is achieved with the integration time of 32 ns and signal to noise ratio (SNR) of 15.3 dB. For the non-line-of-sight (NLOS) outdoor channel, the integration time of 72 ns and SNR of 16.2 dB are needed. The integrated energy to total received energy (IRR) for the best BER performance is about $86\%$.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.144-155
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• 1998

The array weights that will maximize the SNR for any type of noise environment are determined by the function of the antenna design configuration and the directions of receiving target and interference signals. The conventional SLCs(sidelobe cancellers) using the SNR maximization perform worst from the saturation of the receiving system of main channel when the main antenna has pattern with high gain at the arrival angle of strong interference. In this paper, the new SLC is accomplished by using two independent antenna architecture. Main antenna is implemented with adaptive nulling, which is used for rejecting high-power interference primarily. Auxiliary antenna is realized with adaptive array for receiving interference signal to be suppressed completely, which has a characteristics of sufficient gain for every direction. The new SLC is implemented with above both antennas. We show that the new SLC, which consists of the adaptive nulling main antenna and the adaptive array auxiliary antenna, is useful in reducing the effect of strong interference like jammer, because the adaptive nulling at main antenna prevents its receiver and signal processor for saturation by strong interference. The proposed SLC has improved SNR over the conventional SLCs. The improved SNR at sidelobe region is typically more than 7 dB for a given test signal. Moreover, it improves the SNR of about 20 dB under strong interference at mainlobe.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.4
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• pp.381-388
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• 2015

In this paper, a wireless video streaming system is designed and implemented for TV white space applications. It consists of a RF transceiver module, a digital modem, a camera, and a LCD screen. A VGA resolution video is captured by a camera, modulated by modem, and transmitted by RF transceiver module, and finally displayed at a destination 2.6-inch LCD screen. The RF transceiver is based on direct-conversion architecture. Image leakage is improved by low pass filtering LO, which successfully covers the TVWS. Also, DC offset problem is solved by current steering techniques which control common mode level at DAC output node. The output power of the transmitter and the minimum sensitivity of the receiver is +10 dBm and -82 dBm, respectively. The channel bandwidth is tunable among 6, 7 and 8 MHz according to regulations and standards. Digital modem is realized in Kintex-7 FPGA. Data rate is 9 Mbps based on QPSK and 512ch OFDM. A VGA video is successfully streamed through the air by using the developed TV white-space RF communication module.

• Journal of Advanced Navigation Technology
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• v.22 no.6
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• pp.591-601
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• 2018

This paper discusses methods to effectively operates and evaluates an infrastructure system for lane-level positioning based on satellite navigation. The lane-level positioning infrastructure provides correction information on range measurements with integrity information on the correction to a user with a single frequency (cheap) satellite navigation receiver in order to perform lane-level positioning and integrity monitoring on the position estimate. The architecture and configuration of the lane-level positioning system are described from the systematic level in order to provide a comprehensive insight of the system. The operation/evaluation system for the integrated infrastructure is then presented. The evaluation results of the real implemented system are provided. Based on the results, we discuss requirements to increase the system stability from the operation perspective.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.