• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• The Journal of the Acoustical Society of Korea
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• v.27 no.3
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• pp.149-153
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• 2008

General underwater target detection methods adopt short-time FFT for estimate target doppler. This paper proposes the efficient target detection method, instead of conventional FFT, using approximate FFT for distributed sensor network target detection, which requires lighter computations. In the proposed method, we decrease computational rate of FFT by the quantization of received signal. For validation of the proposed method, experiment result which is applied to FFT based active sonar detector and real oceanic data is presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.1-10
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• 2011

Physical modeling has been widely used for sound synthesis since it synthesizes high quality sound which is similar to real-sound for musical instruments. However, physical modeling requires a lot of parameters to synthesize a large number of sounds simultaneously for the musical instrument, preventing its real-time processing. To solve this problem, this paper proposes a single instruction, multiple data (SIMD) based multi-core processor that supports real-time processing of sound synthesis of gayageum which is a representative Korean traditional musical instrument. The proposed SIMD-base multi-core processor consists of 12 processing elements (PE) to control 12 strings of gayageum in which each PE supports modeling of the corresponding string. The proposed SIMD-based multi-core processor can generate synthesized sounds of 12 strings simultaneously after receiving excitation signals and parameters of each string as an input. Experimental results using a sampling reate 44.1 kHz and 16 bits quantization show that synthesis sound using the proposed multi-core processor was very similar to the original sound. In addition, the proposed multi-core processor outperforms commercial processors(TI's TMS320C6416, ARM926EJ-S, ARM1020E) in terms of execution time ($5.6{\sim}11.4{\times}$ better) and energy efficiency (about $553{\sim}1,424{\times}$ better).

• Journal of the Korea Computer Graphics Society
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• v.6 no.4
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• pp.35-42
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• 2000

3D texture mapping generates highly natural visual effects in which objects appear carved from lumps of materials rather than laminated with thin sheets as in 2D texture mapping. Storing 3D texture images in a table for fast mapping computations, instead of evaluating procedures on the fly, however, has been considered impractical due to the extremely high memory requirement. Recently, a practical real-time 3D texture mapping technique was proposed in [11], where they attempt to resolve the potential texture memory problem by compressing 3D textures using a wavelet-based encoding method. In this paper, we consider two other encoding schemes that could also be applied to the compression-based 3D texture mapping. In particular, we extend the vector quantization and FXT1 for 3D texture compression, and compare their performance with the wavelet-based encoding scheme.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.1
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• pp.1-8
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• 2024

On-device AI technology, which can operate AI models at the edge devices to support real-time processing and privacy enhancement, is attracting attention. As intelligent IoT is applied to various industries, services utilizing the on-device AI technology are increasing significantly. However, general deep learning models require a lot of computational resources for inference and learning. Therefore, various lightweighting methods such as quantization and pruning have been suggested to operate deep learning models in embedded edge devices. Among the lightweighting methods, we analyze how to lightweight and apply deep learning models to edge computing devices, focusing on pruning technology in this paper. In particular, we utilize dynamic and static pruning techniques to evaluate the inference speed, accuracy, and memory usage of a lightweight AI vision model. The content analyzed in this paper can be used for intelligent video control systems or video security systems in autonomous vehicles, where real-time processing are highly required. In addition, it is expected that the content can be used more effectively in various IoT services and industries.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2411-2414
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• 2003

In this paper, we present a digital image authentication using semi-fragile watermarking techniques. The algorithm is robust to innocuous manipulations while detecting malicious manipulations. Specifically, the proposed method is designed for the purpose of the real time authentication of an image frame captured from a digital camera due to its easy H/W implementation, security and visible verification. To achieve the semi-fragile characteristics that survive a certain amount of compression, we employ the invariant property of DCT coefficients' quantization proposed by Lin and Chang [1]. The binary watermark bits are generated by exclusive ORing the binary logo with pseudo random binary sequences. Then watermark bits are embedded into the LSBs of pre-quantized DCT coefficients in the medium frequency range. Verification is carried out easily due to visually recognizable pattern of the logo extracted by exclusive ORing the LSBs of the embedded DCT coefficient with pseudo random number seeded by a secret key. By the experiment results, this method is not only robust to JPEG compression but also it detects powerfully alterations of the original image, such as the tempering of images.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.10
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• pp.883-892
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• 2021

This paper provides a process for developing deep learning-based aerial object detection models that can run in realtime on onboard. To improve object detection performance, we pre-process and augment the training data in the training stage. In addition, we perform transfer learning and apply a weighted cross-entropy method to reduce the variations of detection performance for each class. To improve the inference speed, we have generated inference acceleration engines with quantization. Then, we analyze the real-time performance and detection performance on custom aerial image dataset to verify generalization.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.11
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• pp.3761-3779
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• 2022

The performance of existing recognition algorithms for binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK) signals degrade under conditions of low signal-to-noise ratios (SNR). Hence, a novel recognition algorithm based on features in the graph domain is proposed in this study. First, the power spectrum of the squared candidate signal is truncated by a rectangular window. Thereafter, the graph representation of the truncated spectrum is obtained via normalization, quantization, and edge construction. Based on the analysis of the connectivity difference of the graphs under different hypotheses, the sum of degree (SD) of the graphs is utilized as a discriminate feature to classify BPSK and QPSK signals. Moreover, we prove that the SD is a Schur-concave function with respect to the probability vector of the vertices (PVV). Extensive simulations confirm the effectiveness of the proposed algorithm, and its superiority to the listed model-driven-based (MDB) algorithms in terms of recognition performance under low SNRs and computational complexity. As it is confirmed that the proposed method reduces the computational complexity of existing graph-based algorithms, it can be applied in modulation recognition of radar or communication signals in real-time processing, and does not require any prior knowledge about the training sets, channel coefficients, or noise power.