• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.155-162
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• 1999

Various applications of video conferencing are required real-time transmission in order to offer service of best effort in internet. Because the bandwidth of internet changes dynamically, appropriated QoS could not be guaranteed To resolve the problem. available bandwidth between sender and receiver is measured. And according to measured bandwidth, the transmission of multimedia data is controlled In this paper, we propose algorithm of efficient transmission for best QoS in internet According to a present status of network, we measure available bandwidth using feedback RTCP information and change a compression rate to reduce a producing CODEC data. And according to the priority that is measured by packet loss for received RTCP information, we abandon frames indicated as lower weight in transmission buffer of sender.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.766-772
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• 2007

H.264/AVC is a new international standard for the compression of video images, in which a deblocking filter has been adopted to remove blocking artifacts. This paper proposes an efficient architecture of deblocking filter in H.264/AVC. By making good use of data dependence between neighboring $4{\times}4$ blocks, the memory size is reduced and the throughput of the deblocking filter processing is increased. Compared to the conventional deblocking filters, the proposed architecture enhances the performance of deblocking filter processing from 1.75 to 4.23 times. Hence the proposed architecture is able to perform real-time deblocking of high-resolution($2048{\times}1024$) video applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Transactions of the Korean Society of Mechanical Engineers B
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• v.24 no.2
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• pp.153-160
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• 2000

A Particle Image Velocimetry(PIV) algorithm is developed to analyze whole flow field both qualitatively and quantitatively. The practical use of PIV requires the use of fast, reliable, computer-based methods for tracking numerous particles suspended in a flow field. The TSS, NTSS, FFT-Hybrid, which are developed in the area of image compression and coding, are introduced to develop fast vector search algorithm. The numerical solution of the lid-driven cavity flow by the ADI algorithm with the Wachspress Formula is introduced to produce synthetic data for the validation of the tracking algorithms. The algorithms are applied to image data of real flow experiments. The comparisons in CPU time and mean error show, with a small loss of accuracy, CPU time for tracking is reduced considerably.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.183-187
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• 2002

This paper proposes a remote control system that combines computer network and an autonomous mobile robot. We control remotely an autonomous mobile robot with vision via the internet to guide it under unknown environments in the real time. The main feature of this system is that local operators need a World Wide Web browser and a computer connected to the internet communication network and so they can command the robot in a remote location through our Home Page. This system offers an image compression method using motion H.263 concept which reduces large time delay that occurs in network during image transmission.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.45-45
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• 2000

This paper proposes a remote control system that combines computer network and an autonomous mobile robot. We control remotely an autonomous mobile robot with vision via the internet to guide it under unknown environments in the real time. The main feature of this system is that local operators need a World Wide Web browser and a computer connected to the internet communication network and so they can command the robot in a remote location through our Home Page. The hardware architecture of this system consists of an autonomous mobile robot, workstation, and local computers. The software architecture of this system includes the server part for communication between user and robot and the client part for the user interface and a robot control system. The server and client parts are developed using Java language which is suitable to internet application and supports multi-platform. Furthermore, this system offers an image compression method using motion JPEG concept which reduces large time delay that occurs in network during image transmission.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.157-160
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• 2007

System realization and video watermarking using spatial and interframe information is presented in this paper. The system is constructed with DSP processor to process compression and watermark algorithm with real time. Video watermark algorithm is used the watermark insertion using the spatial and interframe. As a results, the processing time of D1 image per frame is 32.1msec in DSP.

• ETRI Journal
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• v.29 no.5
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• pp.655-666
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• 2007

There are nodes and edges in a topological map. Node data has been used as a main source of information for the localization of mobile robots. In contrast, edge data is regarded as a minor source of information, and it has been used in an intuitive and heuristic way. However, edge data also can be used as a good source of information and provide a way to use edge data efficiently. For that purpose, we define a data format which describes the shape of an edge. This format is called local generalized Voronoi graph's angle (LGA). However, the LGA is constituted of too many samples; therefore, real time localization cannot be performed. To reduce the number of samples, we propose a compression method which utilizes wavelet transformation. This method abstracts the LGA by key factors using far fewer samples than the LGA. Experiments show that the LGA accurately describes the shape of the edges and that the key factors preserve most information of the LGA while reducing the number of samples.

• Journal of Korea Game Society
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• v.14 no.4
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• pp.45-52
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• 2014

We cannot load the entire data for high-resolution terrain model to the GPU memory since its size is too big. Out-of-core approaches are commonly used to solve the problem. However, due to limited bandwidth of the secondary storage, it is difficult to render the terrain in real-time. A method that compresses the DEM data with wavelet transform on GPU, and renders the decoded data is suggested. However, it is inefficient since it has to sample the values from textures, convert them to vertices, and generate a mesh periodically. We propose a method to store the approximation coefficients of wavelet compression as vertex attributes and render the terrain by decoding the data on geometric shader. It can reduce the amount of transferring terrain texture since approximation coefficients are given as an attribute of the vertex. Also, it generate meshes without additional upload of terrain texture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.