• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1900-1906
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• 1997

In this paper, the efficient BILBO(named EBILBO) is designed for BIST that is able to batch the testing when circuit is designed on FPGA. The proposed algorithm of batch testing is able to test the normal operation speed with one-pin-count that can control all part of large and complex circuit. PRTPG is used for the test pattern and MISR is used for PSA. The proposed algorithm of batch testing is VHDL coding on behavioral description, so it is easily modified the model of test pattern generation, signature analysis and compression. The EBILBO's area and the performance of designed BIST are evaluated with ISCAS89 benchmark circuit on FPGA. In circuit with above 600 cells, it is shown that area is reduced below 30%, test pattern is flexibly generated about 500K and the fault coverage is from 88.3% to 100%. EBILBO for the proposed batch testing BIST is able to execute concurrently normal and test mode operation in real time to the number of $s+n+(2^s/2^p-1)$ clock(where, in CUT, # of PI;n, # of register, p is order # of polynomial). The proposed algorithm coded with VHDL is made of library, then it well be widely applied to DFT that satisfy the design and test field on sme time.

• Korean Journal of Remote Sensing
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• v.18 no.6
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• pp.359-367
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• 2002

In this paper, a new embedded wavelet packet image coder algorithm is proposed for an effective image coder using correlation between partitioned coefficients. This new algorithm presents parent-child relationship for reducing image reconstruction error using relations between individual frequency sub-bands. By parent-child relationship, every coefficient is partitioned and encoded for the zerotree data structure. It is shown that the proposed wavelet packet image coder algorithm achieves low bit rates and rate-distortion. It also demonstrates higher PSNR under the same bit rate and an improvement in image compression time. The perfect rate control is compared with the conventional method. These results show that the encoding and decoding processes of the proposed coder are simpler and more accurate than the conventional ones for texture images that include many mid and high-frequency elements such as aerial and satellite photograph images. The experimental results imply the possibility that the proposed method can be applied to real-time vision system, on-line image processing and image fusion which require smaller file size and better resolution.

• Coupled systems mechanics
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• v.4 no.4
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• pp.279-295
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• 2015

The article presents a theoretical-experimental approach developed for modeling the coefficient of sliding friction in the dynamic system tool-workpiece in slide diamond burnishing of low-alloy unhardened steels. The experimental setup, implemented on conventional lathe, includes a specially designed device, with a straight cantilever beam as body. The beam is simultaneously loaded by bending (from transverse slide friction force) and compression (from longitudinal burnishing force), which is a reason for geometrical nonlinearity. A method, based on the idea of separation of the variables (time and metric) before establishing the differential equation of motion, has been applied for dynamic modeling of the beam elastic curve. Between the longitudinal (burnishing force) and transverse (slide friction force) forces exists a correlation defined by Coulomb's law of sliding friction. On this basis, an analytical relationship between the beam deflection and the sought friction coefficient has been obtained. In order to measure the deflection of the beam, strain gauges connected in a "full bridge" type of circuit are used. A flexible adhesive is selected, which provides an opportunity for dynamic measurements through the constructed measuring system. The signal is proportional to the beam deflection and is fed to the analog input of USB DAQ board, from where the signal enters in a purposely created virtual instrument which is developed by means of Labview. The basic characteristic of the virtual instrument is the ability to record and visualize in a real time the measured deflection. The signal sampling frequency is chosen in accordance with Nyquist-Shannon sampling theorem. In order to obtain a regression model of the friction coefficient with the participation of the diamond burnishing process parameters, an experimental design with 55 experimental points is synthesized. A regression analysis and analysis of variance have been carried out. The influence of the factors on the friction coefficient is established using sections of the hyper-surface of the friction coefficient model with the hyper-planes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.9
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• pp.1244-1253
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• 2021

In this paper, we propose a method for predicting in advance whether pedestrians will enter the hazardous area after the current time using the pedestrian trajectory prediction method and an efficient simplification method of the trajectory prediction network. In addition, we propose a method to apply KD(Knowledge Distillation) to a small network for real-time operation in an embedded environment. Using the correlation between predicted future paths and hazard zones, we determined whether to enter or not, and applied efficient KD when learning small networks to minimize performance degradation. Experimentally, it was confirmed that the model applied with the simplification method proposed improved the speed by 37.49% compared to the existing model, but led to a slight decrease in accuracy. As a result of learning a small network with an initial accuracy of 91.43% using KD, It was confirmed that it has improved accuracy of 94.76%.

• Smart Structures and Systems
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• v.28 no.6
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• pp.745-760
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• 2021

Dynamic buckling of structure is one of the failure modes that needs to be considered since it may result in catastrophic failure of the structure in a short period of time. For a thin fiber-reinforced polymer (FRP) plate under compression, buckling is an inherent hazard which will be intensified by the existence of defects like holes, cracks, and delamination. On the other hand, the growth of the delamination is another prime concern for thin FRP plates. In the current paper, reinforcing the plates against buckling is realized by using SMA wires in the form of stitches. A numerical framework is proposed to simulate the dynamic instability emphasizing the effect of the SMA stitches in suppressing delamination growth. The suggested algorithm is more accurate than the other methods when considering the transformation point of the SMA wires and the modeling of the cohesive zone using simple and yet reliable technique. The computational design of the method by producing the line by line orders leads to a simple algorithm for simulating the super-elastic behavior. The Lagoudas constitutive model of the SMA material is implemented in the form of user material subroutines (VUMAT). The normal bilinear spring model is used to reproduce the cohesive zone behavior. The nonlinear finite element formulation is programmed into FORTRAN using the Newmark-beta numerical time-integration approach. The obtained results are compared with the results obtained by the finite element method using ABAQUS/Explicit solver. The obtained results by the proposed algorithm and those by ABAQUS are in good agreement.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.155-164
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• 2015

This paper describes a design and implementation of CABAC decoder, which would handle HEVC syntax elements in adaptively pipelined-parallel computation manner. Even though CABAC offers the high compression rate, it is limited in decoding performance due to context-based sequential computation, and strong data dependency between context models, as well as decoding procedure bin by bin. In order to enhance the decoding computation of HEVC CABAC, the flag-type syntax elements are adaptively pipelined by precomputing consecutive flag-type ones; and multi-bin syntax elements are decoded by processing bins in parallel up to three. Further, in order to accelerate Binary Arithmetic Decoder by reducing the critical path delay, the update and renormalization of context modeling are precomputed parallel for the cases of LPS as well as MPS, and then the context modeling renewal is selected by the precedent decoding result. It is simulated that the new HEVC CABAC architecture could achieve the max. performance of 1.01 bins/cycle, which is two times faster with respect to the conventional approach. In ASIC design with 65nm library, the CABAC architecture would handle 224 Mbins/sec, which could decode QFHD HEVC video data in real time.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.91-97
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• 1995

This paper describes the implementation of a multi-channel audio codec for HETV. This codec has the features of the 3/2-stereo plus low frequency enhancement, downward compatibility with the smaller number of channels, backward compatibility with the existing 2/0-stereo system(MPEG-1 audio), and multilingual capability. The encoder of this codec consists of 6-channel analog audio input part with the sampling rate of 48 kHz, 4-channel digital audio input part and three TMS320C40 /DSPs. The encoder implements multi-channel audio compression using a human perceptual psychoacoustic model, and has the bit rate reduction to 384 kbit/s without impairment of subjective quality. The decoder consists of 6-channel analog audio output part, 4-channel digital audio output part, and two TMS320C40 DSPs for a decoding procedure. The decoder analyzes the bit stream received with bit rate of 384 kbit/s from the encoder and reproduces the multi-channel audio signals for analog and digital outputs. The multi-processing of this audio codec using multiple DSPs is ensured by high speed transfer of date between DSPs through coordinating communication port activities with DMA coprocessors. Finally, some technical considerations are suggested to realize the problem of real-time operation, which are found out through the implementation of this codec using the MPEG-2 layer II sudio coding algorithm and the use of the hardware architecture with commercial multiple DSPs.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.37-48
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• 2005

The efficiency of power supply circuits such as DC-DC converters and batteries varies on the trend of the power consumption because their efficiencies are not fixed. To analyze the efficiency of power supply circuits, we need the temporal behavior of the power consumption of the loads, which is dependent on the activity factors of the devices during the operation. Since it is not easy to model every detail of those factors, one of the most accurate power consumption analyses of power supply circuits is measurement of a real system, which is expensive and time consuming. In this paper, we introduce an active load emulator for embedded systems which is capable of power measurement, logging, replaying and synthesis. We adopt a pattern recognition technique for data compression in that long-term behaviors of power consumption consist of numbers of repetitions of short-term behaviors, and the number of short-term behaviors is generally limited to a small number. We also devise a heterogeneous structure of active load elements so that low-speed, high-current active load elements and high-speed, low-current active load elements may emulate large amount and fast changing power consumption of digital systems. For the performance evaluation of our load emulator, we demonstrate power measurement and emulation of a hard drive. As an application of our load emulator, it is used for the analysis of a DC-DC converter efficiency and for the verification of a low-power frequency scaling policy for a real-time task.

• The Journal of the Acoustical Society of Korea
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• v.21 no.6
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• pp.566-575
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• 2002

Low-titrate audio coding enables a number of Internet and mobile multimedia streaming service more efficiently. For the help of next-generation mobile telephone technologies and digital audio/video compression algorithm, we can enjoy the real-time multimedia contents on our mobile devices (cellular phone, PDA notebook, etc). But the limited available bandwidth of mobile communication network prohibits transmitting high-qualify AV contents. In addition, most bandwidth is assigned to transmit video contents. In this paper, we design a novel and simple method for reproducing high frequency components. The spectrum of high frequency components, which are lost by down-sampling, are modeled by the energy rate with low frequency band in Bark scale, and these values are multiplexed with conventional coded bitstream. At the decoder side, the high frequency components are reconstructed by duplicating with low frequency band spectrum at a rate of decoded energy rates. As a result of segmental SNR and MOS test, we convinced that our proposed method enhances the subjective sound quality only 10%∼20% additional bits. In addition, this proposed method can apply all kinds of frequency domain audio compression algorithms, such as MPEG-1/2, AAC, AC-3, and etc.