• Journal of Power Electronics
• /
• v.15 no.4
• /
• pp.861-875
• /
• 2015

This paper presents a wide frequency range LLC resonant controller IC for LED backlight units. In this paper a new phase-domain resonance deviation prevention circuit (RDPC), which covers a wide frequency and input voltage range, is proposed. In addition, a wide range gate clock generator and an automatic dead time generator are proposed. The chip is fabricated using 0.35 μm BCD technology. The die size is 2 x 2 mm2. The frequency of the clock generator ranges from 38 kHz to 400 kHz, and the dead time ranges from 300 ns to 2 μs. The current consumption of the LLC resonant controller IC is 4 mA for a 100 kHz operation frequency using a supply voltage of 15 V.

• Journal of Power Electronics
• /
• v.11 no.3
• /
• pp.271-278
• /
• 2011

This paper presents a LLC resonant controller IC for secondary side control without external active devices to achieve low profile and low cost LED back light units. A gate driving transformer is adopted to isolate the primary side and the secondary side instead of an opto-coupler. A new integrated dimming circuitry is proposed to improve the dynamic current control characteristic and the current density of a LED for the brightness modulation of a large screen LCD. A dual-slope clock generator is proposed to overcome the frequency error due to the under shoot in conventional approaches. This chip is fabricated using 0.35 ${\mu}m$ BCD technology and the die size is $2{\times}2\;mm^2$. The frequency range of the clock generator is from 50 kHz to 500 kHz and the range of the dead time is from 50 ns to 2.2 ${\mu}s$. The efficiency of the LED driving circuit is 97 % and the current consumption is 40 mA for a 100 kHz operation frequency from a 15 V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.4
• /
• pp.88-95
• /
• 2015

This paper presents a new analysis of RF negative resistance (RFNR) circuits, known as a negative resistance generator. For accurate equation analysis of RFNR, this study examined the effects of the gate resistance and the source parasitic capacitance of the transistor. In addition, the input admittance of the conventional equation was calculated by looking into the source-terminal of the transistor, whereas that of the proposed equation was calculated by examining the gate-terminal of the transistor. The proposed equation analysis is more accurate than that of the conventional analysis, especially for higher frequency range. This paper verify the accuracy of the proposed analysis at high frequency range using the simulation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.2A
• /
• pp.129-136
• /
• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• Journal of the Korea Society of Computer and Information
• /
• v.4 no.4
• /
• pp.57-68
• /
• 1999

The purpose of this study is to build a description technique and to make a simulator, which can simulate and verify the behavior of gate level digital system. To get the object code from the input description language, we build a translator. To do this, we used YACC of the UNIX parser generator. and made an intermediate code in the mid-process between translator and simulator to extend the range of application. For experimental models. we used the Full-Adder and Modulo-3 Counter.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.44 no.12
• /
• pp.1103-1111
• /
• 2016

Korea Astronomy and Space Science Institute (KASI) has been operating SLR (Satellite Laser Ranging) system with 2kHz repetition rate for satellite precise orbit and spin determination as well as space geodesy. But the SLR system was improved to be capable of laser ranging with high repetition rate, up to 10kHz by developing new operation software and novel range gate generator, called HSLR-10. The HSLR-10 will contribute to the accurate spin rate determination of geodetic satellites and geodetic research due to its largest repetition rate in the world. In this study, the development methodology and configuration of operation software are addressed, and its validation results are also presented.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.1
• /
• pp.98-105
• /
• 2007

In this paper, we propose a timing detector using suboptimal maximum likelihood method. The proposed method has an simple reference signal generator. Additionally, timing detector's gain of the proposed method is the same to Early-Late gate and ML method. We reveal that tracking range of time tracker is narrow because of using data-decision, that is, tracking range is ${\pm}0.06ns$ for the 4-order Gaussian monocycle with 0.7ns pulse width. Therefore we can find that searcher must have very accurate acquisition procedure. When estimating a performance of time tracker, we consider a jitter in transmitter and receiver's pulse generation process as well as background noise. By using computer simulation, we propose mean/variance of timing detector and tracking process. Also we consider a mobility in tracking process, i.e., timing error modeled ramp function. In order to propose a performance of time tracker, we consider only one correlation demodulator.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.23 no.3
• /
• pp.221-228
• /
• 2020

This paper presents the radar counter jamming algorithm and ground far-field test results for the pull-off deceptive jamming signals like RGPO(Range Gate Pull Off) and VGPO(Velocity Gate Pull Off). We designed the radar counter jamming algorithm according to the characteristics of the deceptive jamming signals. This algorithm is validated by simulation before ground far-field test. The existing X-band AESA radar demonstrator was used to test the proposed algorithm. The proposed algorithm was applied to the radar processor software. The deceptive jamming signals generated using the commercial jamming signal generator. We performed the repeated ground far-field test with the test scenario. Test results show that the proposed counter deceptive jamming algorithm works in the real radar system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.5
• /
• pp.1349-1359
• /
• 1998

In this paper, presented is the result of a digital implementation of a FM stereo composite signal generator. The chip utilizing DDFS(Direct Digital Frequency Synthesizer architecture is implemented using $1.0\mu\textrm{m}$ CMOS gate-array technology thereby replacing analog componentry. To verify the process of generating composite signals a conventional logic simulation method was used. The processed chip was mounted on an evaluation PCB to test and analyze to signals. According to the measurement result obtained by using a 12-bit DAC, the digital FM composite signal generator produces a 74DB spectrally pure signal over its entire tuning range, which is superior to that of analog counterpart by 14dB in it spectral reponse. And further enhancements of the spectral response is expected to be achieved by using a high resolution digital to analog converter, such as a 16-bit DAC. The resulting signals is superior to the signal of the analoy circuitry typically used, in major characteristics such as S/N ratios, accuracy, tuning stability, and signal seperation.

• Journal of the Korean Society of Fisheries and Ocean Technology
• /
• v.24 no.1
• /
• pp.1-6
• /
• 1988

For the purpose of making the detection range of fish detection system more longer and computerizing the system a parametric sound source, a timer and a digitizing circuit for the Apple II computer have been studied. The parametric sound of 5 KHz generated by passing AND gate two signals from carrier signal generator of 200KHz with modulator of 5KHz. This parametric acoustic source of 5KHz difference frequency had more higher directional resolution of 10 degrees than single frequency sound of 200KHz. Peripheral interface adaptor MC 6821 was adopted for interfacing to the Apple II personal computer. The timer consisted of six decade binary coded decimal counters (74 LS 190), and the digitizing circuit consisted of a sample and hold (LF 398) and an A/D converter(ADC 0808). The timer with 10KHz clock pulse had the measuring time from 0.1msec to 100sec. This time measuring range was satisfactory for the aim of the fish finding acoustic system.