• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.2
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• pp.93-106
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• 1998

RS부호의 복호 기법은 전체 통신 시스템의 성능 및 복잡도에 큰 영향을 미친다. 지금까지 RS부호의 복호 기법은 다양한 방법에 있으나Euclid알고리즘과 변환복호기법을 이용한 복호 기법은 오류정정능력이 큰 복호 기법으로 널리 적용되고 있다. 본 논문에서는 오류정정능력이 5이상인 RS부호의 복호 알고리즘에 적용될 수 있는 효율적인 복호 알고리즘을 제시하고, 이를 이용하여 5중 오류 정정(31, 21)RS 부호기 및 복호기를 설계하고VHDL을 사용한 컴퓨터 시뮬레션을 통해서 그 타당성을 검증하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.4B
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• pp.427-436
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• 2001

RS product codes are widely used in digital storage systems. There are lots of decoding strategies for product code for short-length RS codes. Unfortunately many of them cannot be applied to long-length RS product codes because of the complexity of decoder. This paper proposes new decoding strategies which can be used in long length RS product codes.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.3-8
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• 2012

Two-dimensional product code has been studied for correcting burst errors on the storage systems. An RS-LDPC product code consists of an RS code in horizontal direction and an LDPC code in vertical direction. First, we detect the position of burst errors by using RS code, then LDPC code corrects the errors by using the burst error positions. In storage system, long burst errors are occurred by various reason. So, we need a strong code for correcting the long burst errors. RS-LDPC product code is good for long burst errors. However, as the storage density grows the length of the burst errors will be longer. Thus, we propose an LDPC-LDPC product code, it is strong for correcting the very long burst errors. Also, the proposed LDPC-LDPC product code performs better than RS-LDPC product code when the random errors are occurred, because a row direction LDPC code performs better than row direction RS code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.8
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• pp.1477-1484
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• 2015

In this paper, a novel reversible data hiding by using Reed-Solomon (RS) code is proposed for efficient transmission in encryption image. To increase the recovery of data from encrypted image, RS codes are used to encode messages, and then the codewords can be embedded into encrypted image according to encryption key. After receiving encrypted image which embeds the codewords, the receiver firstly decryptes the encrypted image using the encryption key and get metric about codewords containing messages. According to recovery capability of RS codes, better estimation of message is done in data hiding system. Simulation results about two images and two RS codes show that the performances of the proposed schemes are better than ones of the reference scheme.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.10-17
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• 1989

The Berlekamp-Massey algorithm, the method of using the Euclid algorithm, and Fourier transforms over a finite field can be used for the decoding of Reed-Solomon codes (called RS codes). RS codes can also be decoded by the algorithm that was developed by Peterson and refined by the Gorenstein and Zierler. However, the decoding of RS codes using the Peterson-Gorenstein-Zieler algorithm offers sometimes computational or implementation advantages. The decoding procedure of the double-error correcting (31,27) Rs code over the symbol field GF ($2^5$) will be analyized in this paper. The complete analysis, gate array design, and implementation for encoder/decoder pair of (31.27)RS code are performed with a strong theoretical justification.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.7
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• pp.730-738
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• 1992

This paper alms to analyse the performance of frequency hopping /spread spectrum multiple access system by employing the channel with mixture of AWGN, partial band Jamming, fading and user interference. The performance analysis of FH /SSMA system, taking account of frequency 'hit'(user Interference ) which occurs in the presence of multiple user, produces the following numerical results by computing error probability and throughput of each code in two cases whether the side Information about channel is used or not. The numerical results are as follows : When composite interferences coexist In channel, RS code Is significantly superior to convolutional code in terms of performance. Concatenated code provides the same performance as RS code. The above results show that RS code is pertinent as error-correction code.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.34-40
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• 1999

Reed-Solomon(RS) codes have been employed to correct burst errors in applications such as CD-ROM, HDTV, ATM and digital VCRs. For the decoding RS codes, the Berlekamp-Massey algorithm, Euclidean algorithm and modified Euclidean algorithm(MEA) have been developed among which the MEA becomes the most popular decoding scheme. We propose an efficient recursive cell architecture suitable for the MEA. The advantages of the proposed scheme are twofold. First, The proposed architecture uses about 25% less clock cycles required in the MEA operation than[1]. Second, the number of recursive MEA cells can be reduced, when the number of clock cycles spent in the MEA operation is larger than code word length n. thereby buffer requirement for the received words can be reduced. For demonstration, the MEA circurity for (128,124) RS code have been described and the MEA operation is verified through VHDL.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.