• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.3
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• pp.214-220
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• 2022

This paper proposes a test device designed for developing a high-voltage multilayer ceramic capacitor (MLCC). The proposed topology consists of an energy recovery circuit for charging/discharging capacitor, a flyback converter, and a boost converter for supplying power and a bias voltage application to the energy recovery circuit. The energy recovery circuit designed with a half-bridge converter has auxiliary switches operating before the main switches to prevent excessive current from flowing to the main switches. A prototype has been designed to verify the reliability of target capacitors following the voltage fluctuation with a frequency range below 65 kHz. To conduct high root mean square (RMS) current to the capacitor as a load, the MLCC test was conducted after the topology verification was completed through the film capacitor as a load. Through the agreement between the RMS current formula proposed in this paper and the MLCC test results, the possibility of its use was demonstrated for high-voltage MLCC development in the future.

• Journal of Power Electronics
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• v.8 no.4
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• pp.363-370
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• 2008

In this paper, three kinds of PWM strategies for a three-phase current-fed dc/dc converter are proposed and compared in terms of losses and voltage transfer ratio. Each PWM strategy is described graphically and their switching losses are analyzed. With the proposed PWM C strategy, one turn-off switching of each bridge switch is eliminated to reduce switching losses under the same switching frequency. In addition, RMS current through the bridge switches is lowered by using parallel connection between two bridge switches and thus, conduction losses of the switches are reduced. Further, copper losses of the transformer are decreased due to the reduced RMS current of each transformer's winding. Therefore, total losses are minimized and the efficiency of the converter is improved by using the proposed PWM C strategy. Digital signal processor (DSP: TI320LF2407) and a field-programmable gate array (FPGA: EPM7128) board are used to generate PWM patterns for three-phase bridge and clamp MOSFETs. A 500W prototype converter is built and its experimental results verify the validity of the proposed PWM strategies.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.11a
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• pp.377-382
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• 2005

This paper presents two new circuit topologies of DC bus lineside active edge resonant snubber assisted soft-switching PWM full-bridge DC-DC converter acceptable for either utility AC 200V-rms or AC 400V-rms input voltage source. One topology of proposed DC-DC converters is composed of a typical voltage source-fed full-bridge high frequency PWM inverter using DC busline side series power semiconductor switching devices with the aid of a parallel capacitive lossless snubber. All the active power switches in the full-bridge arms and DC busline can achieve ZCS turn-on and ZVS turn-off commutations and the total turn-off switching power losses of all active switches can be reduced for high-frequency switching action. It is proved that the more the switching frequency of full-bridge soft switching inverter increases, the more soft-switching PWM DC-DC converter with a hish frequency transformer link has remarkable advantages for its efficiency and power density as compared with the conventional hard-switching PWM inverter type DC-DC converter

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.150-158
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• 2017

This study proposes a new pulse-width modulation switching pattern for the low conduction loss of a three-level neutral point clamped (NPC)-based dual-active bridge (DAB) converter. The operational principle for a bidirectional power conversion is a phase-shift modulation. The conventional switching method of the three-level NPC-based DAB converter shows a symmetric switching pattern. This method has a disadvantage of high root-mean-square (RMS) value of the coupling inductor current, which leads to high conduction loss. The proposed switching method shows an asymmetrical pattern, which can reduce the RMS value of the inductor current with lower conduction loss than that of the conventional method. The performance of the proposed asymmetrical switching method is theoretically analyzed and practically verified using simulation and experiment.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.4
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• pp.325-331
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• 2022

This study proposes a design method that minimizes a conduction loss of LCC resonant converter under rated condition. Through a simplified analysis of the waveform of the resonant current, the power transfer section and RMS value of the resonant current was analyzed mathematically and graphically. Based on this analysis, the design method that minimizes the RMS value of the resonant current is proposed. To demonstrate this method, this study designed a 7.5 kW (100 V, 75 A) capacitor charger based on LCC resonant converter and the design parameters were chosen according to the process of the design method. Then, the capacitor charger was implemented. An experiment was conducted to measure efficiency while satisfying design specifications under rated conditions. This design method was verified to be effective by achieving 97.7% maximum efficiency and design specifications under rated conditions.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.6
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• pp.496-503
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• 2009

In this paper, a new three-phase interleaved isolated high efficiency boost dc-dc converter with active clamp is proposed. The converter is capable of increased power transfer due to its three-phase power configuration, and it reduces the rms current per phase, thus reducing conduction losses. Further, interleaved operation of three-phase boost converter reduces overall ripple current, which is imposed into fuel cells and realizes smaller sized filter components, increasing effective operating frequency and leading to higher power density. Each output current of three-phase boost converter is combined by the three-phase transformer and flows in the continuous conduction mode by the proposed three-phase PWM strategy. An efficiency of above 96% is mainly achieved by reducing conduction losses and switching losses are reduced by the action of active clamp branches, as well. The proposed converter and three-phase PWM strategy are analyzed, simulated and implemented in hardware. Experimental results are obtained on a 500 W prototype unit, with all of the design verified and analyzed.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.5
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• pp.400-409
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• 2001

A new phase-shifted parallel-input/series-output(PISO) dual converter for tush-power step-up applications has been proposed. Since the proposed converter shows a low switch turn-off voltage stress, switching devices with low conduction loss can be employed in order to improve the power conversion efficiency. Moreover, it features a low output capacitor root-mean-square(RMS) current stress, low input current and output voltage ripple contents, and fast control-to-output dynamics compared to its PWM counterpart. In this paper, the operation of the proposed converter is analyzed in detail and its mathematical models and steady-state solutions are presented. A comparative analysis with the conventional PWM PISO dual converter is also provided. To confirm the operation, features, and validity of the Proposed converter, experimental results from an 800W, 24-350Vdc prototype are presented.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.1
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• pp.66-69
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• 2019

This study proposes a high-efficiency phase-shifted full-bridge (PSFB) converter with a wide input voltage range. The conventional PSFB converter is a useful topology in high-power applications. This converter not only achieves the zero-voltage switching of the primary switches, but also has small RMS current in the primary side. However, because the conventional PSFB converter has large freewheeling current in the primary side when it is designed considering the hold-up time of the converter, such a converter has high conduction loss at the primary switches. To solve this problem, a new PSFB converter is proposed in this study. The experiment is implemented with an input voltage ranging from a 320 V-400 V and an output power specification of 715 W.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.643-645
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• 1999

The conventional high frequency phase-shifted full bridge dc/dc converter has a disadvantage that a circulating current flows through transformer and switching devices during the freewheeling interval. Due to this circulating current, RMS current stress, conduction losses of transformer and switching devices are increased. To alleviate this problem, this paper provides a circulating current free type high frequency soft switching phase-shifted full bridge (FB) dc/dc converter with the modified energy recovery snubber (ERS) attached at the secondary side of transforemr.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.293-301
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• 2011

This paper proposes a bridgeless half-bridge AC-DC converter with high-efficiency. The proposed converter integrates the bridgeless power factor correction (PFC) circuit with the asymmetrical pulse-width modulated (APWM) half-bridge DC-DC converter. It provides the isolated DC output voltage from the AC line voltage without using any full-bridge diode rectifier. Conduction losses are lowered with a simple circuit structure. Switching losses are also reduced by achieving zero-voltage switching (ZVS) of the power switches. By using series-connected two transformers, the proposed converter provides a low-profile and high power density for AC-DC converters. The performance of the proposed converter is verified from a 250 W (48 V / 5.2 A) experimental prototype circuit at $90 \;V_{rms}$ line voltage.