• Title/Summary/Keyword: RFID Block tag

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An implementation of block cipher algorithm HIGHT for mobile applications (모바일용 블록암호 알고리듬 HIGHT의 하드웨어 구현)

  • Park, Hae-Won;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.05a
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    • pp.125-128
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    • 2011
  • This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

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Robust Location Tracking Using a Double Layered Particle Filter (이중 구조의 파티클 필터를 이용한 강인한 위치추적)

  • Yun, Keun-Ho;Kim, Dai-Jin;Bang, Sung-Yang
    • Journal of KIISE:Software and Applications
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    • v.33 no.12
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    • pp.1022-1030
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    • 2006
  • The location awareness is an important part of many ubiquitous computing systems, but a perfect location system does not exist yet in spite of many researches. Among various location tracking systems, we choose the RFID system due to its wide applications. However, the sensed RSSI signal is too sensitive to the direction of a RFID reader antenna, the orientation of a RFID tag, the human interference, and the propagation media situation. So, the existing location tracking method in spite of using the particle filter is not working well. To overcome this shortcoming, we suggest a robust location tracking method with a double layered structure, where the first layer coarsely estimates a tag's location in the block level using a regression technique or the SVM classifier and the second layer precisely computes the tag's location, velocity and direction using the particle filter technique. Its layered structure improves the location tracking performance by restricting the moving degree of hidden variables. Many extensive experiments show that the proposed location tracking method is so precise and robust to be a good choice for implementing the location estimation of a person or an object in the ubiquitous computing. We also validate the usefulness of the proposed location tracking method by implementing it for a real-time people monitoring system in a noisy and complicate workplace.

Design of Low-Area and Low-Power 1-kbit EEPROM (저면적.저전력 1Kb EEPROM 설계)

  • Yu, Yi-Ning;Yang, Hui-Ling;Jin, Li-Yan;Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.4
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    • pp.913-920
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    • 2011
  • In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

The Study of Smart Navigation System development for blind people based on Cortex-A8 Platform include Digital Zoom (Digital Zoom기능을 포함한 Cortex-A8 Platform 기반의 시각장애인용 Smart Navigation System개발에 관한 연구)

  • Han, Seung-Hwan;Kim, Young-kil
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.289-292
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    • 2012
  • Presently, there is the blind of about 20~300,00 people including didn't register in Korea Usually, they used white stick when they walk outside. There is the blind receiving the help of the guide dog but a small number of blind uses due to many composite problems including the cost problem, and etc. Presently, the guidance service aid long for the blind which is commonly used adheres the RFID tag to the white stick. It remains at the level of the extent of making the cover block and RF communication by using this. The recognition distance is short. This is the actual condition in which it is difficult to determine the location of the clear obstacle and size and form, it doesn't become the help which is actually big in the walk of the blinds. Thus, in this paper, the investigation of 'Smart Portable Navigation System' development of the Cortex-A8 Platform base tries to be handled so that the blinds can walk easily.

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