• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3256-3258
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• 1999

Recently contactless ID system has emerged as new ID industry. It's called RF-ID. RF-ID is divided into active RF-ID and passive RF-ID. The passive RF-ID operates without battery and so has no limitation in its operating range and life time. But it needs the RF-OC conversion circuit. It also can be applied to batteryless sensor for many application. This paper presents the study of the RF-OC conversion circuit for batteryless system in high frequency and confirms it by simulation and experiment.

• 전기학회논문지
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• 제68권2호
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• pp.304-309
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• 2019

This paper presents a CMOS RF-to-DC converter for video surveillance disposable IoT applications. It widely harvests RF energy of 3G/4G cellular low-band frequency range by employing a tunable impedance matching network. The proposed converter consists of the differential-drive cross-coupled rectifier and the matching network with a 4-bit capacitor array. The proposed converter is designed using 130-nm standard CMOS process. The designed energy harvester can rectify the RF signals from 700 MHz to 900 MHz. It has a peak RF-to-DC conversion efficiency of 72.25%, 64.97%, and 66.28% at 700 MHz, 800 MHz, and 900 MHz with a load resistance of 10kΩ, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 Proceedings of the Korea Automatic Control Conference, 11th (KACC); Pohang, Korea; 24-26 Oct. 1996
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• pp.255-258
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• 1996

This paper describes a DC voltage controller for the DC power supply which is constructed using the full-bridged MOS-FET DC-to-RF power inverter and rectifier. The full-bridged MOS-FET DC-to-RF inverter consisting of four MOSFET arrays and an output power transformer has a control function which is able to control the RF output power when the widths of the pulse voltages which are fed to four MOS-FET arrays of the fall-bridged inverter are changed using the pulse width control circuit. The power conversion efficiency of the full-bridged MOS-FET DC-to-RF power inverter was approximately 85 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The RF output voltage from the full-bridged MOS-FET DC-to-RF inverter is fed to the rectifier circuit through the output transformer. The rectifier circuit consists of GaAs schottky diodes and filters, each of which is made of a coil and capacitors. The power conversion efficiency of the rectifier circuit was over 80 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The output voltage of the rectifier circuit was changed from 34.7V to 37.6 V when the duty cycles of the pulse voltages were changed from 30 % to 50 %.

• 한국항행학회논문지
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• 제10권2호
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• pp.138-144
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• 2006

본 논문에서는 와이브로와 무선랜 응용을 위한 이중 모우드 FET 믹서를 단일 게이트의 두 개 pHEMT를 캐스코드(cascode)로 연결하여 이중게이트 FET 믹서 형태로 구현하였다. 설계된 이중게이트 믹서는 와이브로와 무선랜 응용에서 DC 전력소모를 최소화하기위해 가변적인 변환이득을 갖도록 최적화되었다. 설계 믹서의 LO-RF간 격리도 특성은 2.3GHz~2.5GHz에서 약 20dB이다. LO신호가 0dBm이고 RF신호가 -50dBm일 때 믹서는 15dB의 변환이득을 갖는다. 수신되는 RF신호가 -50dBm에서 -20dBm까지 증가할 때 변환이득은 15dB에서 -2dB까지 바이어스에 따라 감소하게 된다. 가변 변환이득은 몇 가지 장점이 있다. 즉 IF단에서 AGC의 넓은 동작영역의 부담을 줄일 수 있고, 또한 믹서의 DC전력소모를 약 90% 절약할 수 있다.

• 한국전자파학회논문지
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• 제15권7호
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• pp.730-735
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• 2004

본 논문에서는 WCDMA단말기 직접변환 수신기에서 DC 오프셋 발생원인과 DC 오프셋에 의한 시스템 성능열화에 대해 언급하고, QPSK(Quadrature Phase Shift Keying)변조 방식에서 DC오프셋 값에 의한 성능 열화를 시뮬레이션을 통해 확률 오류에 대한 $E_{b}/N_{o}$ 값으로 나타내었다. DC 오프셋 제어 회로를 추가한 단말기 직접변환 RF 트랜시버 보드를 구현하여 WCDMA(Wideband Code Division Multiple Access) 테스트 베드를 구축하고, DC 오프셋 변화량에 따른 복조기 수신 성능을 $E_{c}/I_{o}$ 값을 이용하여 평가 및 분석하였다. 분석 및 시스템 시험 결과를 통해 시스템 성능열화 방지를 위한 DC 오프셋 관련 최소 성능 요구규격을 제시하였다.

• 한국항행학회논문지
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• 제14권5호
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• pp.655-660
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• 2010

본 논문에서는 무선전력전송을 위한 정류회로의 RF-to-DC 변환효율 개선에 대해 연구하였다. 정류회로는 지역통과 필터, 다이오드 회로, 직류 통과필터로 구성되어 있는데, 이것들 모두가 변환 효율에 영향을 미친다. 시뮬레이션을 통해 이러한 부분들이 어떻게 변환효율에 영향을 주는지 조사를 하였고, 이러한 내용을 바탕으로 10dBm의 저전력에서 약 50%의 변환효율을 갖는 912MHz의 정류회로를 제작하여 특성을 측정하였다.

• 대한전자공학회논문지SD
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• 제43권10호
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• pp.97-103
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• 2006

본 논문에서는 무선 수신기용 down-conversion mixer에서 발생하는 2차 비선형과 DC-offset 문제를 향상시키는 방법을 제시하였다. 제안 된 회로에서는 간단한 수식적인 분석으로부터 2차 혼변조 왜곡 성분과 DC-offset 성분은 duty cycle 조절을 통하여 제거 될 수 있음을 알 수 있었다. 제안 된 방법을 가지고 $0.13{\mu}m$ RF CMOS 공정을 사용하여 출력 저항에 5%의 오차를 어 모의실험을 수행하여 보았다. 실험 결과 출력 저항에 5%의 오차를 주었을 때, IIP2(second-order input intercept point)와 DC-offset은 각각 2.04dBm와 22mV의 값을 가졌으나, 여기에서 제안된 방법을 통하여 IIP2는 38.8dBm로, DC-offset은 $777{\mu}V$로 각각 향상됨을 확인 할 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.113-114
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• 2006

In this paper, dual-gate mixer has been designed and optimized to have variable conversion gain for WiBro and WLAN applications and to save power. With the LO power of 0dBm and RF power of -50dBm, the mixer shows 15dB conversion gain. When RF power increases from -50dBm to -20dBm, the conversion gain decreases to -2dB with bias change. The variable conversion gain can reduce the high dynamic range requirement of AGC burden at IF stage. Also, it can save the dc power dissipation of mixer up to 90%.

• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2441-2446
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• 2018

This paper presents a radio frequency-to-direct current (RF-to-DC) converter for special RF power harvesting application at 915 MHz. The major featured components of the proposed RF-to-DC converter is the combination of a cross-coupled rectifier and an active diode: first, the cross-coupled rectifier boosts the input voltage to desired level, and an active diode blocks the reverse current, respectively. A prototype was implemented using $0.18{\mu}m$ CMOS technology, and the performance was proven from the fact that the targeted RF harvesting system's full-operation with higher power efficiency; even if the system's input power gets lower (e.g., from nominal 0 to min. -12 dBm), the proposed RF-to-DC converter constantly provides 1.47 V, which is exactly the voltage level to drive follow up system components like DC-to-DC converter and so on. And, maximum power conversion efficiency is 82 % calculated from the 0 dBm input power, 2.3 mA load current.

• International journal of advanced smart convergence
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• 제10권3호
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.