• Journal of Convergence for Information Technology
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• v.7 no.2
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• pp.53-58
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• 2017

This paper describes the design of a simulator for analyzing the accuracy of a correlative interferometer(CI) direction finder. CI direction finder is robust to noise, so it is often used in aircraft or ships where complex antenna installation is required, and the direction finding accuracy is very high. When the radio wave is incident at a specific azimuth angle, the phase difference calculated in a noiseless environment and the phase difference measured in a real environment with noise are fused to estimate the largest correlation coefficient as the azimuth angle of the radio wave. The simulator receives RF frequency, the number of antennas, the antenna coordinates, the transmission signal intensity, the bandwidth of the receiver, the gain and the payload effect, and calculates the direction finding accuracy of 0-360 degrees azimuth and 0-60 degree elevation with 0.5 degree. accuracy.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.5
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• pp.11-18
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• 2021

The small radio frequency tracking radar is a tracking system with a radio frequency sensor that identifies a target through all-weather radio frequency signal processing for a target and searches, detects and tracks the target for the major target. In this paper, we describe the development of a board equipped with TMS320C6678 and XILINX FPGA (Field Programmable Gate Array), a high-speed multi-core DSP that acquires target information through all-weather radio frequency and identifies a target through real-time signal processing. We propose DSP-FPGA combination architecture for DSP and FPGA selection and signal processing, and also explain the design of SRIO for high-speed data transmission.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.3
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• pp.141-147
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• 2019

In this paper, a beam pattern performance analysis was performed according to number of array elements and spacing of the phase array antenna. The distance between array elements in an array structure design was reduced due to the electrical length of Ka-band, which increases the number of array elements in applying the aperture. If the number of elements reduce by widening the array distance, the grating lobes of the same size as the main beam will occur in visible region. If the number of array elements should be applied to a system where the number of array elements should be minimized, the analysis was performed on a plan to reduce the number of array elements and minimize degradation of performance, such as beam width and side lobe level.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.9-14
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• 2019

A small millimeter-wave tracking radar is a pulse-based radar that searches, detects, and tracks a target in real time through a TWS (Track While Scan) method for a traps target on the sea with a large RCS running at low speed. It is necessary to develop a board equipped with a high-speed CPU to acquire and track target information through LPRF, DBS, and HRR signal processing techniques for a trap target operating various kinds of dexterous objects such as chaff and decoy, We designed a signal processor structure including DFT (Discrete Fourier Transform) module design that can perform real - time FFT operation using FPGA (Field Programmable Gate Array) and verified the signal processor implemented through performance test.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.4
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• pp.123-127
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• 2021

Millimeter-wave tracking radars should be operated in various environmental restrictions, thus they demand more computing power and smaller size compared to conventional tracking radars. This paper presents the design and implementation of the compact power supply for millimeter-wave tracking radar applications. To meet requirements of low voltage/high current and voltage accuracy for FPGA/DSP digital circuits, Point of Load (POL) converters are used in order to enhance power density and system efficiency. LDO (Low Dropout) is applied for the output voltage under the light load condition, then the single-input-multi-output power supply with max power of 375 W and 8 outputs is developed. The proposed power supply achieves output voltage accuracy of ±2 % and noise level of <50 mVpp % under full load conditions.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.4
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• pp.67-72
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• 2022

This study presents the design of power amplifier (PA) in 60 nm GaN/Si HEMT technology. A customized transistor model enables the designing circuits operating at W-band. The all matching network of the PA was composed of equivalent transformer circuit to reduce matching loss. And then, equivalent transformer is several advantages without any additional inductive devices so that a wideband power characteristic can be achieved. The designed die area is 3900 ㎛ × 2300 ㎛. The designed results at center frequency achieved the small signal gain of 15.9 dB, the saturated output power (Psat) of 29.9 dBm, and the power added efficiency (PAE) of 24.2% at the supply voltage of 12 V.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.2
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• pp.139-147
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• 2023

The compact tracking radar system is a pulsed radar tracking system that searches, detects, and tracks targets in real time against aircraft targets with a small RCS(Radar Cross Section) maneuvering at high speed. This paper describes the development of comprehensive performance test equipment to verify the performance of the radar system in a anechoic chamber environment. Describes the design and manufacture of comprehensive performance test equipment to meet requirements, including the generation of simulated target signals to simulate aircraft target signals to verify performance in the laboratory environment of radar systems. It also describes a GUI(Graphic User Interface) program to check performance through a test in conjunction with the tracking radar system. Verify the comprehensive performance test equipment implemented through the performance test.

• Steel and Composite Structures
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• v.49 no.3
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• pp.337-348
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• 2023

Successive wetting and drying cycles of concrete due to weather changes can endanger the safety of engineering structures over time. Considering wetting and drying cycles in concrete tests can lead to a more correct and reliable design of engineering structures. This study aims to provide a model that can be used to estimate the resistance properties of concrete under different wetting and drying cycles. Complex sample preparation methods, the necessity for highly accurate and sensitive instruments, early sample failure, and brittle samples all contribute to the difficulty of measuring the strength of concrete in the laboratory. To address these problems, in this study, the potential ability of six machine learning techniques, including ANN, SVM, RF, KNN, XGBoost, and NB, to predict the concrete's tensile strength was investigated by applying 240 datasets obtained using the Brazilian test (80% for training and 20% for test). In conducting the test, the effect of additives such as glass and polypropylene, as well as the effect of wetting and drying cycles on the tensile strength of concrete, was investigated. Finally, the statistical analysis results revealed that the XGBoost model was the most robust one with R2 = 0.9155, mean absolute error (MAE) = 0.1080 Mpa, and variance accounted for (VAF) = 91.54% to predict the concrete tensile strength. This work's significance is that it allows civil engineers to accurately estimate the tensile strength of different types of concrete. In this way, the high time and cost required for the laboratory tests can be eliminated.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.103-108
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• 2023

In this paper, a performance enhancement study of an AESA antenna that can be applied to a seeker that serves as the eye of a missile was conducted, and the performance of the antenna was verified through actual measurement. When designing an AESA antenna, the optimization of the active reflection coefficient must be considered during transmission due to the mutual coupling between radiators that inevitably occurs, and the selection of a radiator that can overcome the space limitation of the seeker with a small size/light weight is an important design consideration. Accordingly, optimization in terms of electrical performance and low-profile structure is required through research on array antennas for application to the AESA structure. The radiator designed and measured in this paper was designed as an SFN that can satisfy the low-profile structure while enhancing the performance of a general vivaldi antenna. Through this paper, it was confirmed that SFN has the same broadband characteristics as general vivaldi antennas and has optimized characteristics required for AESA antennas. The structure optimized through simulation confirmed the pattern characteristics and active reflection coefficient characteristics through the fabrication of actual proto-type antennas.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.1
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• pp.97-101
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• 2024

In this paper, we present the implementation of proton beam irradiation test logic and test results for Xilinx's RFSoC FPGA. In addition to the FPGA function, RFSoC is a chip that integrates CPU, ADC, and DAC and is attracting attention in the defense and space industries aimed at reducing the size of the chip. In order to use these chips in a space environment, an analysis of radiation effects was required and radiation mitigation measures were required. Through the proton irradiation test, the logic to measure the radiation effect of RFSoC was designed. Logic for comparing values stored in memory with normal values was implemented, and protons were irradiated to RFSoC to measure SEU generated in the block memory area. To alleviate the occurrence of SEU in other areas, TMR and SEM were applied and designed. Through the test results, we intend to verify this test configuration and establish an environment in which logic design for satellites can be verified in the future.