• 제목/요약/키워드: RC delay

검색결과 113건 처리시간 0.031초

Modeling of RC shear walls strengthened by FRP composites

  • Sakr, Mohammed A.;El-khoriby, Saher R.;Khalifa, Tarek M.;Nagib, Mohammed T.
    • Structural Engineering and Mechanics
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    • 제61권3호
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    • pp.407-417
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    • 2017
  • RC shear walls are considered one of the main lateral resisting members in buildings. In recent years, FRP has been widely utilized in order to strengthen and retrofit concrete structures. A number of experimental studies used CFRP sheets as an external bracing system for retrofitting of RC shear walls. It has been found that the common mode of failure is the debonding of the CFRP-concrete adhesive material. In this study, behavior of RC shear wall was investigated with three different micro models. The analysis included 2D model using plane stress element, 3D model using shell element and 3D model using solid element. To allow for the debonding mode of failure, the adhesive layer was modeled using cohesive surface-to-surface interaction model at 3D analysis model and node-to-node interaction method using Cartesian elastic-plastic connector element at 2D analysis model. The FE model results are validated comparing the experimental results in the literature. It is shown that the proposed FE model can predict the modes of failure due to debonding of CFRP and behavior of CFRP strengthened RC shear wall reasonably well. Additionally, using 2D plane stress model, many parameters on the behavior of the cohesive surfaces are investigated such as fracture energy, interfacial shear stress, partial bonding, proposed CFRP anchor location and using different bracing of CFRP strips. Using two anchors near end of each diagonal CFRP strips delay the end debonding and increase the ductility for RC shear walls.

Cap truss and steel strut to resist progressive collapse in RC frame structures

  • Zahrai, Seyed Mehdi;Ezoddin, Alireza
    • Steel and Composite Structures
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    • 제26권5호
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    • pp.635-647
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    • 2018
  • In order to improve the efficiency of the Reinforced Concrete, RC, structures against progressive collapse, this paper proposes a procedure using alternate path and specific local resistance method to resist progressive collapse in intermediate RC frame structures. Cap truss consists of multiple trusses above a suddenly removed structural element to restrain excessive collapse and provide an alternate path. Steel strut is used as a brace to resist compressive axial forces. It is similar to knee braces in the geometry, responsible for enhancing ductility and preventing shear force localization around the column. In this paper, column removals in the critical position at the first story of two 5 and 10-story regular buildings strengthened using steel strut or cap truss are studied. Based on nonlinear dynamic analysis results, steel strut can only decrease vertical displacement due to sudden removal of the column at the first story about 23%. Cap truss can reduce the average vertical displacement and column axial force transferred to adjacent columns for the studied buildings about 56% and 61%, respectively due to sudden removal of the column. In other words, using cap truss, the axial force in the removed column transfers through an alternate path to adjacent columns to prevent local or general failure or to delay the progressive collapse occurrence.

Versatile UPQC Control System with a Modified Repetitive Controller under Nonlinear and Unbalanced Loads

  • Trinh, Quoc-Nam;Lee, Hong-Hee
    • Journal of Power Electronics
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    • 제15권4호
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    • pp.1093-1104
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    • 2015
  • A standard repetitive controller (RC) is theoretically able to replace a bank of resonant controllers in harmonic signals tracking applications. However, the traditional RC has some drawbacks such as a poor dynamic response and a complex structure to compensate grid frequency deviations for an effective unified power quality conditioner (UPQC) control scheme. In order to solve these problems, an improved RC with an outstanding dynamic response and a simplified grid frequency adaptive scheme is proposed for UPQC control systems in this paper. The control strategy developed for the UPQC has delay time, i.e., one-sixth of a fundamental period (Tp/6), repetitive controllers. As a result, the UPQC system can provide a fast dynamic response along with good compensation performance under both nonlinear and unbalanced loads. Furthermore, to guarantee the excellent performance of the UPQC under grid frequency deviations, a grid frequency adaptive scheme was developed for the RC using a simple first order Padé's approximation. When compared with other approaches, the proposed control method is simpler in structure and requires little computing time. Moreover, the entire control strategy can be easily implemented with a low-cost DSP. The effectiveness of the proposed control method is verified through various experimental tests.

다층 유전체에서의 Interconnection Line에 대한 커패시턴스와 지연시간 계산 방법에 관한 연구 (A Study on Delay Time and Capacitance Calculation for Interconnection Line in Multi-Dielectric Layer)

  • 김한구;곽계달
    • 전자공학회논문지A
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    • 제29A권9호
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    • pp.46-55
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    • 1992
  • 본 논문에서는 다층유전체 구조를 갖는 VLSI interconnection line 에 대한 커페시턴스를 계산하기 위한 방법을 제안한다. 이 방법은 단일 유전체 구조에서 개발한 3차원 직접 적분방법을 확장한 것이다. 다층유전체에 의한 영향은 Green's function을 수정하는 대신에 경계조건을 추가함으로써 고려하였다. 여기서 사용한 경계조건은 line 표면에서는 전위에 대한 식을 사용하였고, 유전체 경계면ㅇ서는 전계에 대한 식을 사용하였다. 이 방법으로부터 얻어진 커패시턴스를 이용하여 다층유전체 구조에서의 interconnection line에 대한 RC 지연시간의 값을 구했다. 이때 사용한 interconnection 물질은 Al과 WSi-이다.

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저 유전 재료의 에칭 공정을 위한 $H_2/N_2$ 가스를 이용한 Capacitively Coupled Plasma 시뮬레이션 (Capacitively Coupled Plasma Simulation for Low-k Materials Etching Process Using $H_2/N_2$ gas)

  • 손채화
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제55권12호
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    • pp.601-605
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    • 2006
  • The resistance-capacitance (RC) delay of signals through interconnection materials becomes a big hurdle for high speed operation of semiconductors which contain multi-layer interconnections in smaller scales with higher integration density. Low-k materials are applied to the inter-metal dielectric (IMD) materials in order to overcome the RC delay. Relaxation continuum (RCT) model that includes neutral-species transport model have developed to model the etching process in a capacitively coupled plasma (CCP) device. We present the parametric study of the modeling results of a two-frequency capacitively coupled plasma (2f-CCP) with $N_2/H_2$ gas mixture that is known as promising one for organic low-k materials etching. For the etching of low-k materials by $N_2/H_2$ plasma, N and H atoms have a big influence on the materials. Moreover the distributions of excited neutral species influence the plasma density and profile. We include the neutral transport model as well as plasma one in the calculation. The plasma and neutrals are calculated self-consistently by iterating the simulation of both species till a spatio-temporal steady state profile could be obtained.

디커플링 방법을 이용한 RC-Coupled 배선의 해석적 지연시간 예측 모델 (An Analytical Switching-Dependent Timing Model for Multi-Coupled VLSI Interconnect lines)

  • 김현식;어영선;심종인
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.439-442
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    • 2004
  • Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

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상위단계 설계 검증을 위한 논리/타이밍 추출 시스템의 설계 (Design of A Logic/Timing Extraction System for Higher-level Design Verification)

  • 이용재;문인호;황선영
    • 전자공학회논문지A
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    • 제30A권2호
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    • pp.76-85
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    • 1993
  • This paper describes the design of a technology-independent logic, function, and timing extraction system from SPICE-like network descriptions. Technology-independent extraction mechanism is provided in the form of technology files containing the rules for constructing logic gates and functional blocks. The designed system can be more effectively used in cell-based design by describing the cells to be extracted. Timing extraction is performed by using a linear RC gate delay model which takes interconnection delay into account. Experimental results show that estimated delay is within 10 percents for logic gate circuits when compared with SPICE. Through higher-level design descriptions obtained by extraction, design cycles can be considerably reduces.

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스위치 레벨 CMOS 지연시간 모델링과 파라미터 추출 (A Switch-Level CMOS Delay Time Modeling and Parameter Extraction)

  • 김경호;이영근;이상헌;박송배
    • 전자공학회논문지A
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    • 제28A권1호
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    • pp.52-59
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    • 1991
  • An effective and accurate delay time model is the key problem in the simulation and timing verification of CMOS logic circuits. We propose a semi-analytic CMOW delay time model taking into account the configuration ratio, the input waveform slope and the load capacitance. This model is based on the Schichman Hodges's DC equations and derived on the optimally weighted switching peak current. The parameters necessary for the model calculation are automatically determined from the program. The proposed model is computationally effective and the error is typically within 10% of the SPICEA results. Compared to the table RC model, the accuracy is inproved over two times in average.

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Hybrid F-NFC에 의한 저속 디젤 기관의 속도 제어 (Speed Control for Low Speed Diesel Engine by Hybrid F-NFC)

  • 최교호;양주호
    • 동력기계공학회지
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    • 제10권4호
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    • pp.159-164
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    • 2006
  • In recent, the marine engine of a large size is being realized a lower speed, longer stroke and a small number of cylinders for the energy saving. Consequently the variation of rotational torque became larger than former days because of the longer delay-time in fuel oil injection process and an increased output per cylinder. It was necessary that algorithms have enough robustness to suppress the variation of the delay-time and the parameter perturbation. This paper shows the structure of hybrid F-NFC against the delay-time and the perturbation of engine parameter as modeling uncertainties, and the design of the robust speed controller by hybrid F-NFC for the engine. And, The Parameter values of linear equation are determined by RC-GA for F-NFS. The hybrid F-NFC is combined the F-NFC and PID controller for filling up each.

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$0.18{\mu}m$ CMOS Technology에 인터커넥트 라인에 의한 지연시간의 게이트 폭에 대한 의존성 분석 (Characterization of the Dependence of Interconnect Line-Induced Delay Time on Gate Width in ${\mu}m$ CMOS Technology)

  • 장명준;이희덕
    • 대한전자공학회논문지SD
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    • 제37권11호
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    • pp.1-8
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    • 2000
  • 본 논문에서는 인터커넥트 라인을 구동하는 CMOS소자의 게이트 폭의 변화에 따라 소자 및 인터커넥트라인에 의한 RC 지연시간이 어떤 특성을 보이는지에 대하여 분석하였다. 인터커넥트 라인의 캐패시턴스 성분만이 주로 나타나는 구조에서는 MOSFET의 크기가 커질수록 전체 지연시간이 감소하는 특성을 보였다. 반면에 인터커넥트 라인의 저항 및 캐패시턴스 성분이 대등하게 지연시간에 영향을 미치는 구조에서는 전체회로의 지연시간이 최소가 되는 MOSFET 크기가 존재함을 수식적으로 제안하고 실험치와 비교하여 잘맞음을 증명하였다.

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