• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.5
• /
• pp.32-38
• /
• 2009

FTT(Fast Fourier Transform) processor is widely used in OFDM(Orthogonal Frequency Division Multiplesing) system. Because of the increased requirement of mobility and bandwidth in the OFDM system, they need large point FTT processor. Since the size of memory which stores the twiddle factor coefficients are proportional to the N of FFT size, we propose a new method by which we can reduce the size of the coefficient memory. In the proposed method, we exploit a counter and unsigned multiplier to generate the twiddle factor indices. To verify the proposed algorithm, we design TFCGs(Twiddle Factor Coefficient Generator) for 1024pint FFTs with R2SDF(Radix-2 Single-Path Delay Feedback), $R2^3SDF,\;R2^3SDF,\;R2^4SDF$ architectures. The size of ROM is reduced to 1/8N. In the case of $R2^4SDF$ architecture, the area and the power are reduced by 57.9%, 57.5% respectively.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.3
• /
• pp.570-576
• /
• 2004

In this paper, we design the IFFT/FFT (Inverse fast Fourier Transform/Fast Fourier Transform) modules for IEEE 802.11a-1999, which is a standard of the High-speed Wireless LAN using the OFDM (Orthogonal Frequency Division Multiplexing). The designed IFFT/FFT is the 64-point FFT to be compatible with IEEE 802.11a and the pipelined architecture which needs neither serial-to-parallel nor parallel-to-serial converter. We compare four types of IFFT/FFT modules for the hardware complexity and operation : R22SDF (Radix-2 Single-path Delay feedback), the R2SDF (Radix-2 Single-path Delay feedback), R2SDF (Radix-4 Single-path Delay Feedback), and R4SDC (Radix-4 Single-path Delay Commutator). In order to minimize the error, we design the IFFT/FFT module to operate with additional decimal parts after butterfly operation. In case of the R22SDF, the IFFT/FFT module has 44,747 gate counts excluding RAMs and the minimized error rate as compared with other types. And we know that the R22SDF has a small hardware structure as compared with other types.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.2
• /
• pp.430-439
• /
• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of the Korean Society of Food Science and Nutrition
• /
• v.33 no.4
• /
• pp.700-704
• /
• 2004

This study was conducted to determine the several structural carbohydrate of 9 kinds of brassica vegetables. The samples were dried at 6$0^{\circ}C$ for 24 hrs and ground to pass a 0.5 mm screen. The crude protein and crude fat contents of brassica vegetables were 2∼3 times higher than those of grain as dry matter basis. However, the crude ash content of brassica vegetables was 7 times higher than that of grain. Total dietary fiber (TDF) was ranged from 24.26% (Narinosa) to 47.33% (Chinensis) as dry matter basis. Insoluble dietary fiber (IDF) was ranged from 17.75% (Narinosa) to 26.81% (Toscana) as dry matter basis. Soluble dietary fiber (SDF) was ranged from 3.20% (Toscana) to 23.45% (Narinosa) as dry matter basis. The correlation of brassica vegetables was r=0.30 between TDF and IDF, r=0.89 between TDF and SDF (p＜0.01), r =0.25 between TDF and CHO, and r=0.29 between DFi and NDF (p＜0.05), respectively.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1221-1224
• /
• 2003

A 64-point R2$^2$ SDF pipeline FFT processor using a new efficient computation sharing multiplier was designed. Computation sharing multiplication specifically targets computation re-use in multiplication of coefficient vector by scalar and is effectively used in DSP(Digital Signal Processing). To reduce the number of multipliers in FFT, we used the proposed computation sharing multiplier. The 64-point pipeline FFT processor was implemented by VHDL and synthesized using Max+PLUSII of Altera. The simulation result shows that the proposed computation sharing multiplier can be reduced to about 17.8% logic cells compared with a conventional multiplier. This processor can operate at 33MHz and calculate a 64-point pipeline FFT in 1.94 $mutextrm{s}$.

• The Korean Journal of Food And Nutrition
• /
• v.7 no.4
• /
• pp.274-283
• /
• 1994

To provide the efficient application scheme of buckwheat dietary fiber and basic information of seed germination, buckwheat(Fagopyrum esculentum Moench) was germinated at 10$^{\circ}C$ for 7 days and the contents and composition of the total dietary fiber(TDF), insoluble dietary fiber(IDF), soluble dietary fiber(SDF) wire examined at 24 hour intervals. The TDF content in ungerminated seeds was 24.86o on dry weight basis. It decreased for the 1st day of germination, but gradually increased for 7 days afterwords. The contents of IDF and SDF in ungerminated seeds were 22.05, 1.42% respectively. The IDF and SDF contents decreased in the initial stage of germination, but then gradually increased. The composition of the IDF and SDF in the TDF during the germination period showed different tendencies. The IDF decreased with germination time until 5 days and then increased. The SDV increased until 5 days and then decreased gradually. The TDF contents obtained by AOAC method were generally higher than those obtained by Prosky method. The TDF contents obtained by the two method, however, were very closely correlated (r=0.9966, p< 0.01) The IDF(X1) and SDF(X2) showed the significant regression equation(p<0.01) with the root length(Y). The equation was Y: -12.6681+0.5089${\times}$ 1 $\div$ 0.6022Xa and R2 was 0.968.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.417-420
• /
• 1999

This paper present the architecture and design of FFT processor for the OFDM modulation. The OFDM modulation have a merit that use frequecncy efficiently and robust ISI. It needs FFR to have fast and large number of points. Moreover, this FFT design has pipeline architecture. R2$^2$SDF architecture for FFT processor has more advantage others. Therefore this paper present FFT processor used R2$^2$SDF architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.11
• /
• pp.33-40
• /
• 2005

This paper describes a design of FFT/IFFT Core(FFT256/2k), which is an essential block in terrestrial DMB modem. It has four operation modes including 256/512/1024/2048-point FFT/IFFT in order to support the Eureka-147 transmission modes. The hybrid architecture, which is composed of R2SDF and R2SDC structure, reduces memory by $62\%$ compared to R2SDC structure, and the SQNR performance is improved by TS_CBFP(Two Step Convergent Block Floating Point). Timing simulation results show that it can operate up to 50MHz(a)2.5-V, resulting that a 2048-point FFT/IFFT can be computed in 41-us. The FFT256/2k core designed in Verilog-HDL has about 68,400 gates and 58,130 RAM. The average power consumption estimated using switching activity is about 113-mW, and the total average SQNR of over 50-dB is achieved. The functionality of the core was fully verified by FPGA implementation.

• Journal of Nutrition and Health
• /
• v.28 no.1
• /
• pp.5-14
• /
• 1995

The present study was performed to investigate the effect of cereal fiber on lipid concentration of liver and serum in rats. Male Sprague-Dawley rats weighing 180$\pm$4g were divided into five groups by completely randomized block design : R, BR, B, W, and F. Each group fed a diet containing 0.7% cholesterol and a kind of cereal among rice(R), brown rice(BR), barley(B), whole wheat(W), and wheat flour(F) for 5 weeks. The results were summarized as follow : 1) Food intake. weight gain and feed efficiency ratio were not significantly different among the groups. 2) Fecal wet weight and dry weight were significantly higher in W group which fed the most amount of IDF(insoluble dietary fiber). 3) The weight of large intestine was significantly heavier in the W group compared to the others. But the weights of liver, stomach and small intestine were not significantly different among the groups. 4) Total lipid. triglyceride(TG) and total cholesterol(TC) content in liver were significantly different among the groups. The values were the lowest in the B group whose intake of SDF(soluble dietary fiber) was the highest 5) TC content in serum was not significantly different among the groups. TG content in serum was significantly lower in the rest groups than in the R group. HDL-c and free-c content in serum were significantly higher in the B group than in the rest groups. HDL-c/LDL-c, free-c/ester-c ratio were the highest in the B group but not significant. Above results show that the dietary fiber contained in cereals has physiological effects and they are different depending on fractions, IDF and SDF.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.3A
• /
• pp.368-376
• /
• 2006

This paper describes a Fcore_GenSim(Parameterized FFT Core Generation & Simulation Program), which can be used as an essential If(Intellectual Property) in various OFDM modem designs. The Fcore_Gensim is composed of two parts, a parameterized core generator(PFFT_CoreGen) that generates Verilog-HDL models of FFT cores, and a fixed-point FFT simulator(FXP_FFTSim) which can be used to estimate the SQNR performance of the generated cores. The parameters that can be specified for core generation are FFT length in the range of 64 ~2048-point and word-lengths of input/output/internal/twiddle data in the range of 8-b "24-b with 2-b step. Total 43,659 FFT cores can be generated by Fcore_Gensim. In addition, CBFP(Convergent Block Floating Point) scaling can be optionally specified. To achieve an optimized hardware and SQNR performance of the generated core, a hybrid structure of R2SDF and R2SDC stages and a hybrid algorithm of radix-2, radix-2/4, radix-2/4/8 are adopted according to FFT length and CBFP scaling.