• Journal of Korea Water Resources Association
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• v.51 no.5
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• pp.383-393
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• 2018

The regional frequency analysis is the method which uses not only sample of target station but also sample of neighborhood stations in which are classified as hydrological homogeneous regions. Consequently, identification of homogeneous regions is a very important process in regional frequency analysis. In this study, homogeneous regions for regional frequency analysis of precipitation were identified by the self-organizing map (SOM) which is one of the artificial neural network. Geographical information and hourly rainfall data set were used in order to perform the SOM. Quantization error and topographic error were computed for identifying the optimal SOM map. As a result, the SOM model organized by $7{\times}6$ array with 42 nodes was selected and the selected stations were classified into 6 clusters for rainfall regional frequency analysis. According to results of the heterogeneity measure, all 6 clusters were identified as homogeneous regions and showed more homogeneous regions compared with the result of previous study.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.5
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• pp.478-491
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• 1987

In this paper, an all Digital Phase-Locked Loop(DPLL) has been propoed, which has reduced the phase error by using a half period sampling in order to improve the performance of the conventional DPLL which tracks the phase of incoming sinusoidal signal once per cycle for the Positive Going Zero crossing(PGZC) of the signal. The proposed DPLL tracks the phase of input signal twice per cycle with two samplers for the PGZC. So the loop has a half reduction of the steady state phase error fluctuation ranges without decreasing the lock-range in a whole, comparing with that of the conventional DPLL. Also, it has been known that the proposed loop is rapidly locked to input signal for the same valves of phase differenc between sucessive samples and quantization level. The analytic results of the proposed loop have been verified by computer simulation for the practically requeired conditions.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.4
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• pp.39-46
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• 2009

In this paper, we propose a full digital capacitive sensing touch key reducing the effects due to the variations of resistance and clock frequency. The proposed circuit consists of two capacitive loads to measure and a resistor between the capacitive loads. The method measures the delays of the resistor and two capacitive loads, respectively. The ratio of the two delays is represented as the ratio of the two capacitive loads and is irrelative to the resistance and the clock frequency if quantization error is disregarded. Experimental results show the proposed scheme efficiently reduces the effects due to the variations of clock frequency and resistance. Further more the method has l.04[pF] resolution and can be used as a touch key.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.3
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• pp.69-80
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• 2015

This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.6
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• pp.87-93
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• 2012

In this paper, we propose an analog-to-digital converter to set the address of a I2C slave chip. The proposed scheme converts a fixed voltage between 0 and VDD to the digital value which can be used as the address of the slave chip. The rising time and the falling time are measured with digital counter in a serially connected RC circuit, while the circuit is being charged and discharged with the voltage to be measured. The ratio of the two measured values is used to get the corresponding digital value. This scheme gives a strong point which is to be implementable all the parts except comparator using digital logic. Although the method utilizes RC circuit, it has no relation with the RC value if the quantization error is disregarded. Experimental result shows that the proposed scheme gives 32-level resolution thus it can be used to configure the address of the I2C slave chip.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.8
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• pp.80-85
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• 2009

In this paper, we propose a full digital capacitive sensing touch key reducing the effects due to the variations of resistance and clock frequency. The proposed circuit consists of two capacitive loads to measure and a resistor between the capacitive loads. The method measures the delays of the resistor and two capacitive loads, respectively. The ratio of the two delays is represented as the ratio of the two capacitive loads and is irrelative to the resistance and the clock frequency if quantization error is disregarded. Experimental results show the proposed scheme efficiently reduces the effects due to the variations of clock frequency and resistance. Further more the method has 1.04[pF] resolution and can be used as a touch key.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.952-960
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• 2012

In the distributed video coding (DVC) system, the difference between the side information and the original Wyner-Ziv frame is corrected using channel codes and the additional parity bits are requested through feedback channel if the error is not corrected. The efficient bit rate control is important to use the DVC system in the band-limited channel, such as mobile communication environments. In this paper, the constant bit rate control method in the encoder of the DVC system is proposed. The coding performance as well as the bit rate is efficiently controlled by the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.348-354
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• 1993

In this research, a multi-tree coder at 9.6Kbits/sec using a novel scheme for adaptation of the short-term coefficients is developed. The overall delay of the tree coder is maintained at 2.5 msec(16 samples at the 6.4KHz sampling frequency). This coder produces good quality speech over ideal channels, and it is very robust to channel errors up to a bit error rate (BER) of $10^{-3}$. This robustness is achieved by using a parallel adaptation scheme in combination with the use of a smoothed version of the received excitation sequence for adaptation of the short-term prediction coefficients. For the multi-tree coder, reconstructed output speech is evaluated using signal-to-quantization noise ratios (SNR), segmental SNRs, and informal listening tests.

• The Journal of the Acoustical Society of Korea
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• v.24 no.6
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• pp.358-364
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• 2005

In this Paper. we present a bitrate scalable speech codec which uses an ITU-T G.723.1 as the baseline coder and encodes the synthesis error signal in an enhancement coder. ITU-T P.862 (PESQ) is used to evaluate the Performance of the bitrate scalable coder. Experiments show that 6.7kbps enhancement layer based on G.723.1 5.3kbps produces the increase of 0.39 in MOS and 5.7kbps enhancement layer based on G.723.1 6.3kbps Produces the increase of 0.267 in MOS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3C
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• pp.322-328
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• 2009

This paper proposes new simplified sum-product (SSP) decoding algorithm to improve BER performance for low-density parity-check codes. The proposed SSP algorithm can replace multiplications and divisions with additions and subtractions without extra computations. In addition, the proposed SSP algorithm can simplify both the In[tanh(x)] and tanh-1 [exp(x)] by using two quantization tables which can reduce tremendous computational complexity. Moreover, the simulation results show that the proposed SSP algorithm can improve about $0.3\;{\sim}\;0.8\;dB$ of BER performance compared with the existing modified sum-product algorithms.