• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.307-310
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• 2005

본 논문은 CMOS 센서의 ISP 전처리 과정 후 최종 화면에 출력하기 위한 효과적인 이미지 스케일 블록을 저전력, 저비용에 맞은 독립된 하드웨어 장치로 설계 하고자 한다. 카메라 센서 이미지 결과를 디스플레이 장치(OSD(On Screen Display)에 맞는 화면의 크기는 CIF(352${\times}$288), QCIF(176${\times}$144) 출력 모드를 사용한다. 최근 DMB 휴대용 멀티미디어 데이터 전송 사이즈 포맷에서도 위와 같은 사이즈를 지원하고 있다. 일반적인 스케일 처리에서는 PC 그래픽 카드(Graphic Card)장치의 지원을 받아서 처리하는 경우가 많다. 또는 CPU의 연산을 통한 CPU 자원을 점유하여 이미지 스케일을 처리하였다. 휴대용 CMOS 센서용에 적합한 독립적으로 처리할 수 있는 이미지 스케일 기능을 하드웨어로 설계하여 효과적인 시스템 운용과 고속 이미지 스케일 처리가 가능한 하드웨어를 설계하는게 목적이다. 이를 구현 하기위해 기존 알고리즘과 제안한 알고리즘을 비교하여 최적화된 알고리즘 적용하여 VHDL설계언어를 이용한 하드웨어 설계 후, ModelSim 6.0a를 이용하여 데이터를 검증한다.

• Journal of Broadcast Engineering
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• v.10 no.4 s.29
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• pp.528-539
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• 2005

The H.264 has been adopted as the video codec for various multimedia services such as DMB and next-generation DVD because of its superior coding performance. However, the reference codec of the standard, the joint model (JM) contains quite a few algorithms which are too complex to be used for the resource-constraint embedded environment. This paper introduces very low-complexity H.264 encoding algorithm which is applicable for the embedded environment. The proposed algorithm was realized by restricting some coding tools on the basis that it should not cause too severe degradation of RD-performance and adding a few early termination and bypass conditions during the motion estimation and mode decision process. In case of encoding of 7.5fps QCIF sequence with 64kbpswith the proposed algorithm, the encoder yields worse PSNRs by 0.4 dB than the standard JM, but requires only $15\%$ of computational complexity and lowers the required memory and power consumption drastically. By porting the proposed H.264 codec into the PDA with Intel PXA255 Processor, we verified the feasibility of the H.264 based MMS(Multimedia Messaging Service) on PDA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• The KIPS Transactions:PartB
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• v.13B no.3 s.106
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• pp.255-274
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• 2006

Moving object boundary is very important for the accurate segmentation of moving object. We extract the moving object boundary from the moving object edge. But the object boundary shows broken boundaries so we develop a novel boundary linking algorithm to link the broken boundaries. The boundary linking algorithm forms a quadrant around the terminating pixel in the broken boundaries and searches for other terminating pixels to link in concentric circles clockwise within a search radius in the forward direction. The boundary linking algorithm guarantees the shortest distance linking. We register the background from the image sequence using the stationary background filtering. We construct two object masks, one object mask from the boundary linking and the other object mask from the initial moving object, and use these two complementary object masks to segment the moving objects. The main contribution of the proposed algorithms is the development of the novel object boundary linking algorithm for the accurate segmentation. We achieve the accurate segmentation of moving object, the segmentation of multiple moving objects, the segmentation of the object which has a hole within the object, the segmentation of thin objects, and the segmentation of moving objects in the complex background using the novel object boundary linking and the background automatically. We experiment the algorithms using standard MPEG-4 test video sequences and real video sequences of indoor and outdoor environments. The proposed algorithms are efficient and can process 70.20 QCIF frames per second and 19.7 CIF frames per second on the average on a Pentium-IV 3.4GHz personal computer for real-time object-based processing.

• Journal of KIISE:Software and Applications
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• v.32 no.2
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• pp.128-139
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• 2005

Moving object boundary is very important for moving object segmentation. But the moving object boundary shows broken boundary We invent a novel space-oriented boundary linking algorithm to link the broken boundary The boundary linking algorithm forms a quadrant around the terminating pixel in the broken boundary and searches forward other terminating pixel to link within a radius. The boundary linking algorithm guarantees shortest distance linking. We also register the background from image sequence. We construct two object masks, one from the result of boundary linking and the other from the registered background, and use these two complementary object masks together for moving object segmentation. We also suppress the moving cast shadow using Roberts gradient operator. The major advantages of the proposed algorithms are more accurate moving object segmentation and the segmentation of the object which has holes in its region using these two object masks. We experiment the algorithms using the standard MPEG-4 test sequences and real video sequence. The proposed algorithms are very efficient and can process QCIF image more than 48 fps and CIF image more than 19 fps using a 2.0GHz Pentium-4 computer.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.508-510
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• 2005

동영상 압축 표준인 H.264/AVC는 압축 효율을 높이기 위해 기존의 표준과는 다른 기법들을 사용함으로 압축률은 높였지만 보다 많은 계산량을 요구한다. 제한된 자원을 가진 임베디드 환경에서는 많은 계산량은 큰 문제점이 된다. DMB를 포함한 대부분의 경우는 이를 하드웨어적으로 구현을 하고 있지만 구현비용과 업데이트의 용의를 위해서 앞으로는 소프트웨어적으로도 구현이 가능해야 할 것이다. 본 논문에서는 H.264/AVC가 임베디드 환경에서 소프트웨어로 구현을 할 경우 그에 대한 성능 명가를 수행하기 위해 실제 임베디드 장비에서 H.264/AVC 복호기와 임베디드 그래픽 라이브러리를 사용해서 재생기를 구현하였고 다양한 종류의 영상을 재생시키는 실험을 하였다. 이러한 실험을 통해 임베디드 상에서 H.264/AVC 재생기는 QCIF 화면을 초당 3프레임 정도를 재생시키는 능력을 보였다. 이는 사용자측면에서는 동영상이라고 느낄 수 없을 정도의 성능이었다. 그러므로 임베디드 환경에서 H.264로 압축된 영상을 사용할 경우에는 H.264의 프로파일이나 레벨 조정 및 프레임 넘김 기법이 필요 할 것으로 추정한다.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.2
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• pp.119-124
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• 2013

Recent increasing demand on the indoor localization requires more advanced and hybrid technology. This paper proposes an application of the hybrid indoor localization method based on a position-coded pattern that can be used with other existing indoor localization techniques such as vision, beacon, or landmark technique. To reduce the pattern-recognition error rate, the error detection and correction algorithm was applied based on Hamming code. The indoor localization experiments based on the proposed algorithm were performed by using a QCIF-grade CMOS sensor and a position-coded pattern with an area of $1.7{\times}1.7mm^2$. The experiments have shown that the position recognition error ratio was less than 0.9 % with 0.4 mm localization accuracy. The results suggest that the proposed method could be feasibly applied for the localization of the indoor mobile service robots.

• ETRI Journal
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• v.25 no.6
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• pp.489-502
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• 2003

This paper presents an MPEG-4 video codec, called MoVa, for video coding applications that adopts 3G-324M. We designed MoVa to be optimal by embedding a cost-effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG-4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment.

• Proceedings of the Korea Contents Association Conference
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• 2006.11a
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• pp.520-523
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• 2006

Lately, development of multimedia industry has multimedia data serviced through various wire wireless communicating environment. These multimedia data is displayed on the device of various sizes such as mobile telephone, PDA, notebook, PC. Therefore, there has needed to resize multimedia data appropriate to the screen size of user's display device. In this paper, we propose the method to resizing H.264 videos sequence fitting to the screen size of user's display device. The existing most methods reduce the size of video sequence, but this paper proposes the upsampling method. The results show the proposed method upsamples video sequences without blocking effects.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2008.11a
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• pp.131-134
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• 2008

H.264/AVC 부호화 표준은 움직임 벡터를 부호화하기 위해 인접 블록이 가지는 다수의 움직임 벡터 중에서 확률적으로 해당 움직임 벡터와 가장 유사한 중간값을 예측 움직임 벡터로 사용한다. 이러한 방법은 다수의 움직임 벡터 중에서 어떤 움직임 벡터가 예측값으로 사용되었는지에 대한 추가 정보 없이 비트량을 효과적으로 감소시킬 수 있는 장점이 있으나, 중간값을 이용한 예측 움직임 벡터는 해당 움직임 벡터를 부호화하는데 소요되는 비트량을 항상 최소로 만드는 최적 예측값이 아니라는 단점이 있다. 이러한 문제를 해결하기 위해 다수의 인접 블록이 가지는 움직임 벡터 중에서 특정 움직임 벡터가 예측값으로 사용되었는지 표현하는 정보를 복호화기에 알려주도록 하여 항상 최적의 예측 움직임 벡터를 선택함으로써 부호화 효율을 향상시킬 수 있으나, 이에 대한 추가 정보를 부호화해야 하는 문제점이 발생하게 된다. 본 논문에서는 부호화기가 부호화 효율 측면에서 가장 우수한 움직임 벡터를 예측값으로 선택하고, 이를 복호화기가 스스로 예측함으로써 인접 블록이 가지는 다수의 움직임 벡터 중에서 특정 움직임 벡터가 예측값으로 사용되었는지에 대한 정보없이 움직임 벡터 부호화에 소요되는 비트량을 효과적으로 감소시키는 움직임 벡터 부호화 방법을 제안한다. 제안한 부호화기는 율-왜곡 측면에서 가장 우수한 예측 움직임 벡터를 선택하고, 복호화기는 부호화기가 선택한 예측 움직임 벡터를 정합 기술을 사용하여 스스로 예측한다. 실험 결과는 제안 방법이 QCIF 및 CIF 영상에서 약 2.2%의 전체 비트량을 감소시킬 수 있음을 보여준다.