• Journal of Digital Convergence
• /
• v.10 no.5
• /
• pp.215-222
• /
• 2012

A smart phone has functions of both telephone and computer. The wide spread use of smart phones has sharply increased the demand for mobile commerce. The smart phone based mobile services are available anytime, anywhere. In commercial transactions, a digital signature scheme is used to make legally binding signature to prove both integrity of commercial document and verification of the signer. Smart phones are more risky compared with personal computers on the problems of how to protect privacy information. It's also easy to let proxy user to authenticate instead of the smart phone owner. In existing password or token based schemes, the ID is not physically bound to the owner. Thus, those schemes can not solve the problem of proxy authentication. To utilize the smart phone as the platform of mobile commerce, a study on the new type of authentication scheme is needed where the scheme should provide protocol to get legally binding signature and not to authenticate proxy user. In this paper, we create the mobile ID by using both the USIM and voice template of the smart phone owner. We also design and implement the user authentication scheme based on the mobile ID.

• Journal of Korea Multimedia Society
• /
• v.13 no.4
• /
• pp.594-600
• /
• 2010

Many studies are DDoS in Internet network, but the study is the fact that is not enough in a voice network. Therefore, we designed the extended TRW algorithm that was a DDoS attack traffic detection algorithm for the voice network which used an IP data network to solve upper problems in this article and evaluated it. The algorithm that is proposed in this paper analyzes TRW algorithm to detect existing DDoS attack in Internet network and, design connection and end connection to apply to a voice network, define probability function to count this. For inspect the algorithm, Set a threshold and using NS-2 Simulator. We measured detection rate by an attack traffic type and detection time by attack speed. At the result of evaluation 4.3 seconds for detection when transmitted INVITE attack packets per 0.1 seconds and 89.6% performance because detected 13,453 packet with attack at 15,000 time when transmitted attack packet.

• Journal of IKEEE
• /
• v.23 no.1
• /
• pp.58-67
• /
• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.11
• /
• pp.12-17
• /
• 2009

This paper presents a tag emulator for a UHF band RFID system. The tag emulator supports the 1800-6C and EPC global class 1 generation 2 standards. The transmitted signal from a reader is generated using the PIE coding and ASK modulation methods. Signals of a tag are from the FM0 coding and ASK modulation methods. The ARM7 processor carries out the overall control of the system and signal analysis of incoming data. The verification of the tag emulator employs the application platform implemented in C++. Users can define parameter values for protocol during the application run. The tag emulator presented in this paper allows evaluating various design alternatives of the target RFID system in real applications.

• Journal of Advanced Navigation Technology
• /
• v.28 no.3
• /
• pp.254-261
• /
• 2024

Accurate guidance during landing and take-off is important, and instrument landing system (ILS) has been used for stability and verification. Regular inspections are conducted for stable operation, and there is research to perform inspection using drones in addition to ground vehicles and measurement aircraft. Using SDR and single board computer, which can receive wide frequency range, we designed a small system that receives and processes localizer signals through GNU Radio. To check signal processing characteristics through GNU Radio, we simulated with MATLAB Simulink and confirmed the theoretical values. Difference in depth of modulation (DDM) and approach angle can be calculated when the aircraft enters the runway. And GNU Radio implemented real-time signal processing wirelessly using transmission control protocol (TCP). This gives the results within the error of 0.5% when the aircraft entered the runway center line and 0.27% for the angle of 1° degree. Compared to the inspecting and maintaining ILS signals using aircraft or ground vehicles, it is possible to implement a receiving system using small SDR that can be mounted for drone.

• Transactions of the KSME C: Technology and Education
• /
• v.4 no.1
• /
• pp.3-10
• /
• 2016

Heat pump unit performance is represented by the COP(Coefficient of Performance) and expressed by the one point design condition according to KS C 9306. However, when heat pump operated to the real buildings, the simulations are changed continuously according to the actual weather conditions, the building load and heat pump source conditions. The purpose of this paper is to evaluate the APF(Annual performance factor) for a climate dependent building integrated air-to-air heat pump system in major cities in Korea. TRNSYS simulation tool with an international MV standard based IPMVP 4.4.2 was utilized to perform the annual performance analysis. The APF with the multi-performance data based method was calculated as 2.29 for Daejeon residential building case while Busan residential building case appeared as the highest with 2.36.

• Journal of Astronomy and Space Sciences
• /
• v.20 no.4
• /
• pp.339-350
• /
• 2003

Engineering qualification model payload for a communications and broadcasting satellite(CBS) was developed by ETRI from May, 2000 to April, 2003. For. the purpose of functional test and verification of the payload, a real-time hardware-in-the-loop(HITL) CBS simulator(CBSSIM) was also developed. We assumed that the spacecraft platform for the CBSSIM is a geostationary communication satellite using momentum bias three-axis stabilization control technique based on Koreasat. The payload hardware is combined with CBSSIM via Power, Command and Telemetry System(PCTS) of Electrical Ground Support Equipment(EGSE). CBSSIM is connected with PCTS by TCP/IP and the payload is combined with PCTS by MIL-STD-1553B protocol and DC harness. This simulator runs under the PC-based simulation environment with Windows 2000 operating system. The satellite commands from the operators are transferred to the payload or bus subsystem models through the real-time process block in the simulator. Design requirements of the CBSSIM are to operate in real-time and generate telemetry. CBSSIM provides various graphic monitoring interfaces and control functions and supports both pre-launch and after-launch of a communication satellite system. In this paper, the HITL simulator system including CBSSIM, communications payload and PCTS as the medium of interface between CBSSIM and communications payload will be described in aspects of the system architecture, spacecraft models, and simulator operation environment.

• Journal of the Institute of Convergence Signal Processing
• /
• v.15 no.2
• /
• pp.70-75
• /
• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.8
• /
• pp.33-44
• /
• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.8
• /
• pp.95-101
• /
• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.